232 lines
7.3 KiB
Plaintext
Executable file
232 lines
7.3 KiB
Plaintext
Executable file
=====================================================================
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Freescale MPIC Interrupt Controller Node
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Copyright (C) 2010,2011 Freescale Semiconductor Inc.
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=====================================================================
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The Freescale MPIC interrupt controller is found on all PowerQUICC
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and QorIQ processors and is compatible with the Open PIC. The
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notable difference from Open PIC binding is the addition of 2
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additional cells in the interrupt specifier defining interrupt type
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information.
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: Shall include "fsl,mpic". Freescale MPIC
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controllers compatible with this binding have Block
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Revision Registers BRR1 and BRR2 at offset 0x0 and
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0x10 in the MPIC.
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical
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offset and length of the device's registers within the
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CCSR address space.
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- interrupt-controller
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Usage: required
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Value type: <empty>
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Definition: Specifies that this node is an interrupt
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controller
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- #interrupt-cells
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Usage: required
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Value type: <u32>
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Definition: Shall be 2 or 4. A value of 2 means that interrupt
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specifiers do not contain the interrupt-type or type-specific
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information cells.
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- #address-cells
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Usage: required
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Value type: <u32>
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Definition: Shall be 0.
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- pic-no-reset
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Usage: optional
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Value type: <empty>
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Definition: The presence of this property specifies that the
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MPIC must not be reset by the client program, and that
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the boot program has initialized all interrupt source
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configuration registers to a sane state-- masked or
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directed at other cores. This ensures that the client
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program will not receive interrupts for sources not belonging
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to the client. The presence of this property also mandates
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that any initialization related to interrupt sources shall
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be limited to sources explicitly referenced in the device tree.
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- big-endian
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Usage: optional
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Value type: <empty>
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If present the MPIC will be assumed to be big-endian. Some
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device-trees omit this property on MPIC nodes even when the MPIC is
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in fact big-endian, so certain boards override this property.
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- single-cpu-affinity
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Usage: optional
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Value type: <empty>
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If present the MPIC will be assumed to only be able to route
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non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).
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- last-interrupt-source
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Usage: optional
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Value type: <u32>
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Some MPICs do not correctly report the number of hardware sources
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in the global feature registers. If specified, this field will
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override the value read from MPIC_GREG_FEATURE_LAST_SRC.
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INTERRUPT SPECIFIER DEFINITION
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Interrupt specifiers consists of 4 cells encoded as
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follows:
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<1st-cell> interrupt-number
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Identifies the interrupt source. The meaning
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depends on the type of interrupt.
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Note: If the interrupt-type cell is undefined
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(i.e. #interrupt-cells = 2), this cell
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should be interpreted the same as for
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interrupt-type 0-- i.e. an external or
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normal SoC device interrupt.
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<2nd-cell> level-sense information, encoded as follows:
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0 = low-to-high edge triggered
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1 = active low level-sensitive
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2 = active high level-sensitive
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3 = high-to-low edge triggered
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<3rd-cell> interrupt-type
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The following types are supported:
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0 = external or normal SoC device interrupt
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The interrupt-number cell contains
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the SoC device interrupt number. The
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type-specific cell is undefined. The
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interrupt-number is derived from the
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MPIC a block of registers referred to as
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the "Interrupt Source Configuration Registers".
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Each source has 32-bytes of registers
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(vector/priority and destination) in this
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region. So interrupt 0 is at offset 0x0,
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interrupt 1 is at offset 0x20, and so on.
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1 = error interrupt
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The interrupt-number cell contains
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the SoC device interrupt number for
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the error interrupt. The type-specific
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cell identifies the specific error
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interrupt number.
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2 = MPIC inter-processor interrupt (IPI)
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The interrupt-number cell identifies
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the MPIC IPI number. The type-specific
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cell is undefined.
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3 = MPIC timer interrupt
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The interrupt-number cell identifies
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the MPIC timer number. The type-specific
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cell is undefined.
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<4th-cell> type-specific information
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The type-specific cell is encoded as follows:
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- For interrupt-type 1 (error interrupt),
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the type-specific cell contains the
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bit number of the error interrupt in the
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Error Interrupt Summary Register.
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EXAMPLE 1
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/*
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* mpic interrupt controller with 4 cells per specifier
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*/
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mpic: pic@40000 {
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compatible = "fsl,mpic";
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interrupt-controller;
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#interrupt-cells = <4>;
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#address-cells = <0>;
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reg = <0x40000 0x40000>;
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};
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EXAMPLE 2
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/*
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* The MPC8544 I2C controller node has an internal
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* interrupt number of 27. As per the reference manual
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* this corresponds to interrupt source configuration
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* registers at 0x5_0560.
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*
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* The interrupt source configuration registers begin
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* at 0x5_0000.
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*
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* To compute the interrupt specifier interrupt number
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*
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* 0x560 >> 5 = 43
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*
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* The interrupt source configuration registers begin
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* at 0x5_0000, and so the i2c vector/priority registers
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* are at 0x5_0560.
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*/
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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EXAMPLE 3
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/*
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* Definition of a node defining the 4
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* MPIC IPI interrupts. Note the interrupt
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* type of 2.
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*/
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ipi@410a0 {
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compatible = "fsl,mpic-ipi";
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reg = <0x40040 0x10>;
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interrupts = <0 0 2 0
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1 0 2 0
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2 0 2 0
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3 0 2 0>;
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};
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EXAMPLE 4
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/*
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* Definition of a node defining the MPIC
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* global timers. Note the interrupt
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* type of 3.
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*/
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timer0: timer@41100 {
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compatible = "fsl,mpic-global-timer";
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reg = <0x41100 0x100 0x41300 4>;
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interrupts = <0 0 3 0
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1 0 3 0
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2 0 3 0
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3 0 3 0>;
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};
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EXAMPLE 5
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/*
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* Definition of an error interrupt (interrupt type 1).
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* SoC interrupt number is 16 and the specific error
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* interrupt bit in the error interrupt summary register
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* is 23.
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*/
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memory-controller@8000 {
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compatible = "fsl,p4080-memory-controller";
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reg = <0x8000 0x1000>;
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interrupts = <16 2 1 23>;
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};
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