64 lines
2.5 KiB
Plaintext
Executable file
64 lines
2.5 KiB
Plaintext
Executable file
* Power Management Controller
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Properties:
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- compatible: "fsl,<chip>-pmc".
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"fsl,mpc8349-pmc" should be listed for any chip whose PMC is
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compatible. "fsl,mpc8313-pmc" should also be listed for any chip
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whose PMC is compatible, and implies deep-sleep capability.
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"fsl,mpc8548-pmc" should be listed for any chip whose PMC is
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compatible. "fsl,mpc8536-pmc" should also be listed for any chip
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whose PMC is compatible, and implies deep-sleep capability.
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"fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
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compatible; all statements below that apply to "fsl,mpc8548-pmc" also
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apply to "fsl,mpc8641d-pmc".
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Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
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bit assignments are indicated via the sleep specifier in each device's
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sleep property.
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- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
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is the PMC block, and the second resource is the Clock Configuration
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block.
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For devices compatible with "fsl,mpc8548-pmc", the first resource
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is a 32-byte block beginning with DEVDISR.
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- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first
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resource is the PMC block interrupt.
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- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices,
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this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
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a wakeup source from deep sleep.
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Sleep specifiers:
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fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit
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that is set in the cell, the corresponding bit in SCCR will be saved
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and cleared on suspend, and restored on resume. This sleep controller
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supports disabling and resuming devices at any time.
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fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
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which will be ORed into PMCDR upon suspend, and cleared from PMCDR
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upon resume. The first two cells are as described for fsl,mpc8578-pmc.
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This sleep controller only supports disabling devices during system
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sleep, or permanently.
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fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
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first of which will be ORed into DEVDISR (and the second into
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DEVDISR2, if present -- this cell should be zero or absent if the
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hardware does not have DEVDISR2) upon a request for permanent device
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disabling. This sleep controller does not support configuring devices
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to disable during system sleep (unless supported by another compatible
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match), or dynamically.
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Example:
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power@b00 {
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compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
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reg = <0xb00 0x100 0xa00 0x100>;
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interrupts = <80 8>;
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};
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