163 lines
5.9 KiB
Plaintext
Executable file
163 lines
5.9 KiB
Plaintext
Executable file
===================
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RISC-V CPU Bindings
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===================
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The device tree allows to describe the layout of CPUs in a system through
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the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
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defining properties for every cpu.
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Bindings for CPU nodes follow the Devicetree Specification, available from:
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https://www.devicetree.org/specifications/
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with updates for 32-bit and 64-bit RISC-V systems provided in this document.
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===========
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Terminology
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===========
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This document uses some terminology common to the RISC-V community that is not
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widely used, the definitions of which are listed here:
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* hart: A hardware execution context, which contains all the state mandated by
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the RISC-V ISA: a PC and some registers. This terminology is designed to
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disambiguate software's view of execution contexts from any particular
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microarchitectural implementation strategy. For example, my Intel laptop is
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described as having one socket with two cores, each of which has two hyper
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threads. Therefore this system has four harts.
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=====================================
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cpus and cpu node bindings definition
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=====================================
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The RISC-V architecture, in accordance with the Devicetree Specification,
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requires the cpus and cpu nodes to be present and contain the properties
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described below.
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- cpus node
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Description: Container of cpu nodes
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The node name must be "cpus".
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A cpus node must define the following properties:
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- #address-cells
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Usage: required
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Value type: <u32>
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Definition: must be set to 1
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- #size-cells
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Usage: required
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Value type: <u32>
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Definition: must be set to 0
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- cpu node
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Description: Describes a hart context
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PROPERTIES
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- device_type
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Usage: required
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Value type: <string>
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Definition: must be "cpu"
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- reg
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Usage: required
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Value type: <u32>
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Definition: The hart ID of this CPU node
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- compatible:
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Usage: required
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Value type: <stringlist>
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Definition: must contain "riscv", may contain one of
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"sifive,rocket0"
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- mmu-type:
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Usage: optional
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Value type: <string>
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Definition: Specifies the CPU's MMU type. Possible values are
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"riscv,sv32"
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"riscv,sv39"
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"riscv,sv48"
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- riscv,isa:
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Usage: required
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Value type: <string>
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Definition: Contains the RISC-V ISA string of this hart. These
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ISA strings are defined by the RISC-V ISA manual.
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Example: SiFive Freedom U540G Development Kit
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---------------------------------------------
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This system contains two harts: a hart marked as disabled that's used for
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low-level system tasks and should be ignored by Linux, and a second hart that
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Linux is allowed to run on.
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <1000000>;
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cpu@0 {
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clock-frequency = <1600000000>;
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compatible = "sifive,rocket0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <16384>;
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next-level-cache = <&L15 &L0>;
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reg = <0>;
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riscv,isa = "rv64imac";
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status = "disabled";
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L10: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@1 {
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clock-frequency = <1600000000>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&L15 &L0>;
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reg = <1>;
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riscv,isa = "rv64imafdc";
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status = "okay";
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tlb-split;
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L13: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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Example: Spike ISA Simulator with 1 Hart
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----------------------------------------
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This device tree matches the Spike ISA golden model as run with `spike -p1`.
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cpus {
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cpu@0 {
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device_type = "cpu";
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reg = <0x00000000>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "riscv,sv48";
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clock-frequency = <0x3b9aca00>;
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interrupt-controller {
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#interrupt-cells = <0x00000001>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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}
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}
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}
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