147 lines
4.3 KiB
Plaintext
Executable file
147 lines
4.3 KiB
Plaintext
Executable file
Mediatek AFE PCM controller for mt2701
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Required properties:
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- compatible: should be one of the followings.
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- "mediatek,mt2701-audio"
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- "mediatek,mt7622-audio"
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- interrupts: should contain AFE and ASYS interrupts
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- interrupt-names: should be "afe" and "asys"
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- power-domains: should define the power domain
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- clocks: Must contain an entry for each entry in clock-names
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See ../clocks/clock-bindings.txt for details
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- clock-names: should have these clock names:
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"infra_sys_audio_clk",
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"top_audio_mux1_sel",
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"top_audio_mux2_sel",
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"top_audio_a1sys_hp",
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"top_audio_a2sys_hp",
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"i2s0_src_sel",
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"i2s1_src_sel",
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"i2s2_src_sel",
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"i2s3_src_sel",
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"i2s0_src_div",
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"i2s1_src_div",
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"i2s2_src_div",
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"i2s3_src_div",
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"i2s0_mclk_en",
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"i2s1_mclk_en",
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"i2s2_mclk_en",
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"i2s3_mclk_en",
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"i2so0_hop_ck",
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"i2so1_hop_ck",
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"i2so2_hop_ck",
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"i2so3_hop_ck",
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"i2si0_hop_ck",
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"i2si1_hop_ck",
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"i2si2_hop_ck",
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"i2si3_hop_ck",
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"asrc0_out_ck",
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"asrc1_out_ck",
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"asrc2_out_ck",
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"asrc3_out_ck",
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"audio_afe_pd",
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"audio_afe_conn_pd",
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"audio_a1sys_pd",
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"audio_a2sys_pd",
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"audio_mrgif_pd";
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- assigned-clocks: list of input clocks and dividers for the audio system.
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See ../clocks/clock-bindings.txt for details.
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- assigned-clocks-parents: parent of input clocks of assigned clocks.
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- assigned-clock-rates: list of clock frequencies of assigned clocks.
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Must be a subnode of MediaTek audsys device tree node.
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See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
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Example:
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audsys: audio-subsystem@11220000 {
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compatible = "mediatek,mt2701-audsys", "syscon";
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...
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afe: audio-controller {
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compatible = "mediatek,mt2701-audio";
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "afe", "asys";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
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clocks = <&infracfg CLK_INFRA_AUDIO>,
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<&topckgen CLK_TOP_AUD_MUX1_SEL>,
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<&topckgen CLK_TOP_AUD_MUX2_SEL>,
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<&topckgen CLK_TOP_AUD_48K_TIMING>,
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<&topckgen CLK_TOP_AUD_44K_TIMING>,
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<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
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<&audsys CLK_AUD_I2SO1>,
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<&audsys CLK_AUD_I2SO2>,
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<&audsys CLK_AUD_I2SO3>,
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<&audsys CLK_AUD_I2SO4>,
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<&audsys CLK_AUD_I2SIN1>,
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<&audsys CLK_AUD_I2SIN2>,
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<&audsys CLK_AUD_I2SIN3>,
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<&audsys CLK_AUD_I2SIN4>,
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<&audsys CLK_AUD_ASRCO1>,
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<&audsys CLK_AUD_ASRCO2>,
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<&audsys CLK_AUD_ASRCO3>,
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<&audsys CLK_AUD_ASRCO4>,
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<&audsys CLK_AUD_AFE>,
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<&audsys CLK_AUD_AFE_CONN>,
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<&audsys CLK_AUD_A1SYS>,
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<&audsys CLK_AUD_A2SYS>,
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<&audsys CLK_AUD_AFE_MRGIF>;
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clock-names = "infra_sys_audio_clk",
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"top_audio_mux1_sel",
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"top_audio_mux2_sel",
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"top_audio_a1sys_hp",
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"top_audio_a2sys_hp",
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"i2s0_src_sel",
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"i2s1_src_sel",
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"i2s2_src_sel",
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"i2s3_src_sel",
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"i2s0_src_div",
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"i2s1_src_div",
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"i2s2_src_div",
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"i2s3_src_div",
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"i2s0_mclk_en",
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"i2s1_mclk_en",
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"i2s2_mclk_en",
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"i2s3_mclk_en",
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"i2so0_hop_ck",
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"i2so1_hop_ck",
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"i2so2_hop_ck",
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"i2so3_hop_ck",
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"i2si0_hop_ck",
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"i2si1_hop_ck",
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"i2si2_hop_ck",
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"i2si3_hop_ck",
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"asrc0_out_ck",
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"asrc1_out_ck",
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"asrc2_out_ck",
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"asrc3_out_ck",
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"audio_afe_pd",
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"audio_afe_conn_pd",
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"audio_a1sys_pd",
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"audio_a2sys_pd",
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"audio_mrgif_pd";
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assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
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<&topckgen CLK_TOP_AUD_MUX2_SEL>,
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<&topckgen CLK_TOP_AUD_MUX1_DIV>,
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<&topckgen CLK_TOP_AUD_MUX2_DIV>;
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assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
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<&topckgen CLK_TOP_AUD2PLL_90M>;
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assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
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};
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};
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