113 lines
3.7 KiB
Plaintext
Executable file
113 lines
3.7 KiB
Plaintext
Executable file
* ARM architected timer
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ARM cores may have a per-core architected timer, which provides per-cpu timers,
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or a memory mapped architected timer, which provides up to 8 frames with a
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physical and optional virtual timer per frame.
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The per-core architected timer is attached to a GIC to deliver its
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per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
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to deliver its interrupts via SPIs.
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** CP15 Timer node properties:
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- compatible : Should at least contain one of
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"arm,armv7-timer"
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"arm,armv8-timer"
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- interrupts : Interrupt list for secure, non-secure, virtual and
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hypervisor timers, in that order.
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- clock-frequency : The frequency of the main counter, in Hz. Should be present
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only where necessary to work around broken firmware which does not configure
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CNTFRQ on all CPUs to a uniform correct value. Use of this property is
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strongly discouraged; fix your firmware unless absolutely impossible.
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- always-on : a boolean property. If present, the timer is powered through an
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always-on power domain, therefore it never loses context.
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- fsl,erratum-a008585 : A boolean property. Indicates the presence of
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QorIQ erratum A-008585, which says that reading the counter is
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unreliable unless the same value is returned by back-to-back reads.
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This also affects writes to the tval register, due to the implicit
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counter read.
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- hisilicon,erratum-161010101 : A boolean property. Indicates the
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presence of Hisilicon erratum 161010101, which says that reading the
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counters is unreliable in some cases, and reads may return a value 32
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beyond the correct value. This also affects writes to the tval
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registers, due to the implicit counter read.
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** Optional properties:
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- arm,cpu-registers-not-fw-configured : Firmware does not initialize
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any of the generic timer CPU registers, which contain their
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architecturally-defined reset values. Only supported for 32-bit
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systems which follow the ARMv7 architected reset values.
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- arm,no-tick-in-suspend : The main counter does not tick when the system is in
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low-power system suspend on some SoCs. This behavior does not match the
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Architecture Reference Manual's specification that the system counter "must
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be implemented in an always-on power domain."
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Example:
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timer {
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compatible = "arm,cortex-a15-timer",
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"arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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clock-frequency = <100000000>;
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};
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** Memory mapped timer node properties:
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- compatible : Should at least contain "arm,armv7-timer-mem".
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- clock-frequency : The frequency of the main counter, in Hz. Should be present
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only when firmware has not configured the MMIO CNTFRQ registers.
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- reg : The control frame base address.
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Note that #address-cells, #size-cells, and ranges shall be present to ensure
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the CPU can address a frame's registers.
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A timer node has up to 8 frame sub-nodes, each with the following properties:
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- frame-number: 0 to 7.
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- interrupts : Interrupt list for physical and virtual timers in that order.
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The virtual timer interrupt is optional.
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- reg : The first and second view base addresses in that order. The second view
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base address is optional.
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- status : "disabled" indicates the frame is not available for use. Optional.
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Example:
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timer@f0000000 {
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compatible = "arm,armv7-timer-mem";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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reg = <0xf0000000 0x1000>;
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clock-frequency = <50000000>;
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frame@f0001000 {
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frame-number = <0>
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interrupts = <0 13 0x8>,
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<0 14 0x8>;
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reg = <0xf0001000 0x1000>,
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<0xf0002000 0x1000>;
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};
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frame@f0003000 {
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frame-number = <1>
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interrupts = <0 15 0x8>;
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reg = <0xf0003000 0x1000>;
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};
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};
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