114 lines
4.4 KiB
Plaintext
Executable file
114 lines
4.4 KiB
Plaintext
Executable file
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About this document
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===================
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Some notes about Marvell's NAND controller available in PXA and Armada 370/XP
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SoC (aka NFCv1 and NFCv2), with an emphasis on the latter.
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NFCv2 controller background
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===========================
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The controller has a 2176 bytes FIFO buffer. Therefore, in order to support
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larger pages, I/O operations on 4 KiB and 8 KiB pages is done with a set of
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chunked transfers.
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For instance, if we choose a 2048 data chunk and set "BCH" ECC (see below)
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we'll have this layout in the pages:
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------------------------------------------------------------------------------
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| 2048B data | 32B spare | 30B ECC || 2048B data | 32B spare | 30B ECC | ... |
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------------------------------------------------------------------------------
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The driver reads the data and spare portions independently and builds an internal
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buffer with this layout (in the 4 KiB page case):
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------------------------------------------
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| 4096B data | 64B spare |
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------------------------------------------
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Also, for the READOOB command the driver disables the ECC and reads a 'spare + ECC'
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OOB, one per chunk read.
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-------------------------------------------------------------------
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| 4096B data | 32B spare | 30B ECC | 32B spare | 30B ECC |
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-------------------------------------------------------------------
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So, in order to achieve reading (for instance), we issue several READ0 commands
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(with some additional controller-specific magic) and read two chunks of 2080B
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(2048 data + 32 spare) each.
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The driver accommodates this data to expose the NAND core a contiguous buffer
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(4096 data + spare) or (4096 + spare + ECC + spare + ECC).
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ECC
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===
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The controller has built-in hardware ECC capabilities. In addition it is
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configurable between two modes: 1) Hamming, 2) BCH.
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Note that the actual BCH mode: BCH-4 or BCH-8 will depend on the way
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the controller is configured to transfer the data.
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In the BCH mode the ECC code will be calculated for each transferred chunk
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and expected to be located (when reading/programming) right after the spare
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bytes as the figure above shows.
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So, repeating the above scheme, a 2048B data chunk will be followed by 32B
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spare, and then the ECC controller will read/write the ECC code (30B in
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this case):
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------------------------------------
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| 2048B data | 32B spare | 30B ECC |
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------------------------------------
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If the ECC mode is 'BCH' then the ECC is *always* 30 bytes long.
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If the ECC mode is 'Hamming' the ECC is 6 bytes long, for each 512B block.
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So in Hamming mode, a 2048B page will have a 24B ECC.
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Despite all of the above, the controller requires the driver to only read or
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write in multiples of 8-bytes, because the data buffer is 64-bits.
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OOB
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===
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Because of the above scheme, and because the "spare" OOB is really located in
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the middle of a page, spare OOB cannot be read or write independently of the
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data area. In other words, in order to read the OOB (aka READOOB), the entire
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page (aka READ0) has to be read.
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In the same sense, in order to write to the spare OOB the driver has to write
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an *entire* page.
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Factory bad blocks handling
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===========================
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Given the ECC BCH requires to layout the device's pages in a split
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data/OOB/data/OOB way, the controller has a view of the flash page that's
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different from the specified (aka the manufacturer's) view. In other words,
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Factory view:
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-----------------------------------------------
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| Data |x OOB |
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-----------------------------------------------
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Driver's view:
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-----------------------------------------------
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| Data | OOB | Data x | OOB |
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-----------------------------------------------
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It can be seen from the above, that the factory bad block marker must be
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searched within the 'data' region, and not in the usual OOB region.
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In addition, this means under regular usage the driver will write such
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position (since it belongs to the data region) and every used block is
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likely to be marked as bad.
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For this reason, marking the block as bad in the OOB is explicitly
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disabled by using the NAND_BBT_NO_OOB_BBM option in the driver. The rationale
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for this is that there's no point in marking a block as bad, because good
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blocks are also 'marked as bad' (in the OOB BBM sense) under normal usage.
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Instead, the driver relies on the bad block table alone, and should only perform
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the bad block scan on the very first time (when the device hasn't been used).
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