371 lines
13 KiB
C
Executable file
371 lines
13 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ALPHA_PGTABLE_H
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#define _ALPHA_PGTABLE_H
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#include <asm-generic/4level-fixup.h>
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/*
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* This file contains the functions and defines necessary to modify and use
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* the Alpha page table tree.
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*
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* This hopefully works with any standard Alpha page-size, as defined
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* in <asm/page.h> (currently 8192).
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*/
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#include <linux/mmzone.h>
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#include <asm/page.h>
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#include <asm/processor.h> /* For TASK_SIZE */
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#include <asm/machvec.h>
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#include <asm/setup.h>
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struct mm_struct;
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struct vm_area_struct;
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/* Certain architectures need to do special things when PTEs
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* within a page table are directly modified. Thus, the following
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* hook is made available.
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*/
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#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
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#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
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/* PMD_SHIFT determines the size of the area a second-level page table can map */
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#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3))
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* Entries per page directory level: the Alpha is three-level, with
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* all levels having a one-page page table.
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*/
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#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
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#define PTRS_PER_PMD (1UL << (PAGE_SHIFT-3))
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#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-3))
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#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
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#define FIRST_USER_ADDRESS 0UL
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/* Number of pointers that fit on a page: this will go away. */
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#define PTRS_PER_PAGE (1UL << (PAGE_SHIFT-3))
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#ifdef CONFIG_ALPHA_LARGE_VMALLOC
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#define VMALLOC_START 0xfffffe0000000000
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#else
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#define VMALLOC_START (-2*PGDIR_SIZE)
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#endif
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#define VMALLOC_END (-PGDIR_SIZE)
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/*
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* OSF/1 PAL-code-imposed page table bits
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*/
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#define _PAGE_VALID 0x0001
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#define _PAGE_FOR 0x0002 /* used for page protection (fault on read) */
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#define _PAGE_FOW 0x0004 /* used for page protection (fault on write) */
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#define _PAGE_FOE 0x0008 /* used for page protection (fault on exec) */
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#define _PAGE_ASM 0x0010
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#define _PAGE_KRE 0x0100 /* xxx - see below on the "accessed" bit */
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#define _PAGE_URE 0x0200 /* xxx */
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#define _PAGE_KWE 0x1000 /* used to do the dirty bit in software */
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#define _PAGE_UWE 0x2000 /* used to do the dirty bit in software */
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/* .. and these are ours ... */
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#define _PAGE_DIRTY 0x20000
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#define _PAGE_ACCESSED 0x40000
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/*
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* NOTE! The "accessed" bit isn't necessarily exact: it can be kept exactly
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* by software (use the KRE/URE/KWE/UWE bits appropriately), but I'll fake it.
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* Under Linux/AXP, the "accessed" bit just means "read", and I'll just use
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* the KRE/URE bits to watch for it. That way we don't need to overload the
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* KWE/UWE bits with both handling dirty and accessed.
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*
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* Note that the kernel uses the accessed bit just to check whether to page
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* out a page or not, so it doesn't have to be exact anyway.
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*/
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#define __DIRTY_BITS (_PAGE_DIRTY | _PAGE_KWE | _PAGE_UWE)
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#define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_KRE | _PAGE_URE)
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#define _PFN_MASK 0xFFFFFFFF00000000UL
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#define _PAGE_TABLE (_PAGE_VALID | __DIRTY_BITS | __ACCESS_BITS)
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#define _PAGE_CHG_MASK (_PFN_MASK | __DIRTY_BITS | __ACCESS_BITS)
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/*
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* All the normal masks have the "page accessed" bits on, as any time they are used,
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* the page is accessed. They are cleared only by the page-out routines
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*/
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#define PAGE_NONE __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOR | _PAGE_FOW | _PAGE_FOE)
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#define PAGE_SHARED __pgprot(_PAGE_VALID | __ACCESS_BITS)
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#define PAGE_COPY __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
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#define PAGE_READONLY __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
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#define PAGE_KERNEL __pgprot(_PAGE_VALID | _PAGE_ASM | _PAGE_KRE | _PAGE_KWE)
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#define _PAGE_NORMAL(x) __pgprot(_PAGE_VALID | __ACCESS_BITS | (x))
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#define _PAGE_P(x) _PAGE_NORMAL((x) | (((x) & _PAGE_FOW)?0:_PAGE_FOW))
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#define _PAGE_S(x) _PAGE_NORMAL(x)
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/*
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* The hardware can handle write-only mappings, but as the Alpha
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* architecture does byte-wide writes with a read-modify-write
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* sequence, it's not practical to have write-without-read privs.
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* Thus the "-w- -> rw-" and "-wx -> rwx" mapping here (and in
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* arch/alpha/mm/fault.c)
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*/
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/* xwr */
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#define __P000 _PAGE_P(_PAGE_FOE | _PAGE_FOW | _PAGE_FOR)
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#define __P001 _PAGE_P(_PAGE_FOE | _PAGE_FOW)
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#define __P010 _PAGE_P(_PAGE_FOE)
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#define __P011 _PAGE_P(_PAGE_FOE)
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#define __P100 _PAGE_P(_PAGE_FOW | _PAGE_FOR)
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#define __P101 _PAGE_P(_PAGE_FOW)
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#define __P110 _PAGE_P(0)
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#define __P111 _PAGE_P(0)
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#define __S000 _PAGE_S(_PAGE_FOE | _PAGE_FOW | _PAGE_FOR)
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#define __S001 _PAGE_S(_PAGE_FOE | _PAGE_FOW)
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#define __S010 _PAGE_S(_PAGE_FOE)
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#define __S011 _PAGE_S(_PAGE_FOE)
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#define __S100 _PAGE_S(_PAGE_FOW | _PAGE_FOR)
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#define __S101 _PAGE_S(_PAGE_FOW)
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#define __S110 _PAGE_S(0)
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#define __S111 _PAGE_S(0)
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/*
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* pgprot_noncached() is only for infiniband pci support, and a real
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* implementation for RAM would be more complicated.
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*/
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#define pgprot_noncached(prot) (prot)
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/*
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* BAD_PAGETABLE is used when we need a bogus page-table, while
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* BAD_PAGE is used for a bogus page.
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*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern pte_t __bad_page(void);
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extern pmd_t * __bad_pagetable(void);
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extern unsigned long __zero_page(void);
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#define BAD_PAGETABLE __bad_pagetable()
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#define BAD_PAGE __bad_page()
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#define ZERO_PAGE(vaddr) (virt_to_page(ZERO_PGE))
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/* number of bits that fit into a memory pointer */
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#define BITS_PER_PTR (8*sizeof(unsigned long))
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/* to align the pointer to a pointer address */
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#define PTR_MASK (~(sizeof(void*)-1))
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/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
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#define SIZEOF_PTR_LOG2 3
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/* to find an entry in a page-table */
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#define PAGE_PTR(address) \
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((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
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/*
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* On certain platforms whose physical address space can overlap KSEG,
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* namely EV6 and above, we must re-twiddle the physaddr to restore the
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* correct high-order bits.
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*
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* This is extremely confusing until you realize that this is actually
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* just working around a userspace bug. The X server was intending to
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* provide the physical address but instead provided the KSEG address.
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* Or tried to, except it's not representable.
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*
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* On Tsunami there's nothing meaningful at 0x40000000000, so this is
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* a safe thing to do. Come the first core logic that does put something
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* in this area -- memory or whathaveyou -- then this hack will have
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* to go away. So be prepared!
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*/
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#if defined(CONFIG_ALPHA_GENERIC) && defined(USE_48_BIT_KSEG)
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#error "EV6-only feature in a generic kernel"
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#endif
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#if defined(CONFIG_ALPHA_GENERIC) || \
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(defined(CONFIG_ALPHA_EV6) && !defined(USE_48_BIT_KSEG))
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#define KSEG_PFN (0xc0000000000UL >> PAGE_SHIFT)
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#define PHYS_TWIDDLE(pfn) \
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((((pfn) & KSEG_PFN) == (0x40000000000UL >> PAGE_SHIFT)) \
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? ((pfn) ^= KSEG_PFN) : (pfn))
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#else
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#define PHYS_TWIDDLE(pfn) (pfn)
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#endif
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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#ifndef CONFIG_DISCONTIGMEM
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#define page_to_pa(page) (((page) - mem_map) << PAGE_SHIFT)
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#define pte_pfn(pte) (pte_val(pte) >> 32)
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#define pte_page(pte) pfn_to_page(pte_pfn(pte))
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#define mk_pte(page, pgprot) \
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({ \
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pte_t pte; \
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\
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pte_val(pte) = (page_to_pfn(page) << 32) | pgprot_val(pgprot); \
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pte; \
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})
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#endif
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extern inline pte_t pfn_pte(unsigned long physpfn, pgprot_t pgprot)
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{ pte_t pte; pte_val(pte) = (PHYS_TWIDDLE(physpfn) << 32) | pgprot_val(pgprot); return pte; }
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extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
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extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
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{ pmd_val(*pmdp) = _PAGE_TABLE | ((((unsigned long) ptep) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
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extern inline void pgd_set(pgd_t * pgdp, pmd_t * pmdp)
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{ pgd_val(*pgdp) = _PAGE_TABLE | ((((unsigned long) pmdp) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
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extern inline unsigned long
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pmd_page_vaddr(pmd_t pmd)
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{
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return ((pmd_val(pmd) & _PFN_MASK) >> (32-PAGE_SHIFT)) + PAGE_OFFSET;
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}
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#ifndef CONFIG_DISCONTIGMEM
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#define pmd_page(pmd) (mem_map + ((pmd_val(pmd) & _PFN_MASK) >> 32))
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#define pgd_page(pgd) (mem_map + ((pgd_val(pgd) & _PFN_MASK) >> 32))
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#endif
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extern inline unsigned long pgd_page_vaddr(pgd_t pgd)
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{ return PAGE_OFFSET + ((pgd_val(pgd) & _PFN_MASK) >> (32-PAGE_SHIFT)); }
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extern inline int pte_none(pte_t pte) { return !pte_val(pte); }
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extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_VALID; }
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extern inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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pte_val(*ptep) = 0;
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}
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extern inline int pmd_none(pmd_t pmd) { return !pmd_val(pmd); }
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extern inline int pmd_bad(pmd_t pmd) { return (pmd_val(pmd) & ~_PFN_MASK) != _PAGE_TABLE; }
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extern inline int pmd_present(pmd_t pmd) { return pmd_val(pmd) & _PAGE_VALID; }
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extern inline void pmd_clear(pmd_t * pmdp) { pmd_val(*pmdp) = 0; }
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extern inline int pgd_none(pgd_t pgd) { return !pgd_val(pgd); }
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extern inline int pgd_bad(pgd_t pgd) { return (pgd_val(pgd) & ~_PFN_MASK) != _PAGE_TABLE; }
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extern inline int pgd_present(pgd_t pgd) { return pgd_val(pgd) & _PAGE_VALID; }
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extern inline void pgd_clear(pgd_t * pgdp) { pgd_val(*pgdp) = 0; }
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/*
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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extern inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_FOW); }
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extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
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extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
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extern inline int pte_special(pte_t pte) { return 0; }
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extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) |= _PAGE_FOW; return pte; }
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extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(__DIRTY_BITS); return pte; }
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extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~(__ACCESS_BITS); return pte; }
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extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) &= ~_PAGE_FOW; return pte; }
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extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= __DIRTY_BITS; return pte; }
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extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= __ACCESS_BITS; return pte; }
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extern inline pte_t pte_mkspecial(pte_t pte) { return pte; }
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#define PAGE_DIR_OFFSET(tsk,address) pgd_offset((tsk),(address))
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/* to find an entry in a kernel page-table-directory */
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#define pgd_offset_k(address) pgd_offset(&init_mm, (address))
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/* to find an entry in a page-table-directory. */
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#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
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#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
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/*
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* The smp_read_barrier_depends() in the following functions are required to
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* order the load of *dir (the pointer in the top level page table) with any
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* subsequent load of the returned pmd_t *ret (ret is data dependent on *dir).
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*
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* If this ordering is not enforced, the CPU might load an older value of
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* *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for
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* more details.
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*
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* Note that we never change the mm->pgd pointer after the task is running, so
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* pgd_offset does not require such a barrier.
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*/
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/* Find an entry in the second-level page table.. */
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extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
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{
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pmd_t *ret = (pmd_t *) pgd_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
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smp_read_barrier_depends(); /* see above */
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return ret;
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}
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/* Find an entry in the third-level page table.. */
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extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address)
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{
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pte_t *ret = (pte_t *) pmd_page_vaddr(*dir)
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+ ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1));
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smp_read_barrier_depends(); /* see above */
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return ret;
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}
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#define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr))
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#define pte_unmap(pte) do { } while (0)
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extern pgd_t swapper_pg_dir[1024];
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/*
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* The Alpha doesn't have any external MMU info: the kernel page
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* tables contain all the necessary information.
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*/
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extern inline void update_mmu_cache(struct vm_area_struct * vma,
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unsigned long address, pte_t *ptep)
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{
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}
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/*
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* Non-present pages: high 24 bits are offset, next 8 bits type,
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* low 32 bits zero.
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*/
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extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
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{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }
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#define __swp_type(x) (((x).val >> 32) & 0xff)
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#define __swp_offset(x) ((x).val >> 40)
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#define __swp_entry(type, off) ((swp_entry_t) { pte_val(mk_swap_pte((type), (off))) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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#ifndef CONFIG_DISCONTIGMEM
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#define kern_addr_valid(addr) (1)
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#endif
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
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#define pmd_ERROR(e) \
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printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
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extern void paging_init(void);
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#include <asm-generic/pgtable.h>
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/*
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* No page table caches to initialise
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*/
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#define pgtable_cache_init() do { } while (0)
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/* We have our own get_unmapped_area to cope with ADDR_LIMIT_32BIT. */
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#define HAVE_ARCH_UNMAPPED_AREA
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#endif /* _ALPHA_PGTABLE_H */
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