196 lines
6.3 KiB
C
Executable file
196 lines
6.3 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* linux/arch/alpha/kernel/pci_impl.h
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*
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* This file contains declarations and inline functions for interfacing
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* with the PCI initialization routines.
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*/
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struct pci_dev;
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struct pci_controller;
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struct pci_iommu_arena;
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/*
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* We can't just blindly use 64K for machines with EISA busses; they
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* may also have PCI-PCI bridges present, and then we'd configure the
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* bridge incorrectly.
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*
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* Also, we start at 0x8000 or 0x9000, in hopes to get all devices'
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* IO space areas allocated *before* 0xC000; this is because certain
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* BIOSes (Millennium for one) use PCI Config space "mechanism #2"
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* accesses to probe the bus. If a device's registers appear at 0xC000,
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* it may see an INx/OUTx at that address during BIOS emulation of the
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* VGA BIOS, and some cards, notably Adaptec 2940UW, take mortal offense.
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*/
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#define EISA_DEFAULT_IO_BASE 0x9000 /* start above 8th slot */
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#define DEFAULT_IO_BASE 0x8000 /* start at 8th slot */
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/*
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* We try to make the DEFAULT_MEM_BASE addresses *always* have more than
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* a single bit set. This is so that devices like the broken Myrinet card
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* will always have a PCI memory address that will never match a IDSEL
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* address in PCI Config space, which can cause problems with early rev cards.
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*/
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/*
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* An XL is AVANTI (APECS) family, *but* it has only 27 bits of ISA address
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* that get passed through the PCI<->ISA bridge chip. Although this causes
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* us to set the PCI->Mem window bases lower than normal, we still allocate
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* PCI bus devices' memory addresses *below* the low DMA mapping window,
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* and hope they fit below 64Mb (to avoid conflicts), and so that they can
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* be accessed via SPARSE space.
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*
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* We accept the risk that a broken Myrinet card will be put into a true XL
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* and thus can more easily run into the problem described below.
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*/
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#define XL_DEFAULT_MEM_BASE ((16+2)*1024*1024) /* 16M to 64M-1 is avail */
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/*
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* APECS and LCA have only 34 bits for physical addresses, thus limiting PCI
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* bus memory addresses for SPARSE access to be less than 128Mb.
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*/
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#define APECS_AND_LCA_DEFAULT_MEM_BASE ((16+2)*1024*1024)
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/*
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* Because MCPCIA and T2 core logic support more bits for
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* physical addresses, they should allow an expanded range of SPARSE
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* memory addresses. However, we do not use them all, in order to
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* avoid the HAE manipulation that would be needed.
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*/
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#define MCPCIA_DEFAULT_MEM_BASE ((32+2)*1024*1024)
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#define T2_DEFAULT_MEM_BASE ((16+1)*1024*1024)
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/*
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* Because CIA and PYXIS have more bits for physical addresses,
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* they support an expanded range of SPARSE memory addresses.
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*/
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#define DEFAULT_MEM_BASE ((128+16)*1024*1024)
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/* ??? Experimenting with no HAE for CIA. */
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#define CIA_DEFAULT_MEM_BASE ((32+2)*1024*1024)
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#define IRONGATE_DEFAULT_MEM_BASE ((256*8-16)*1024*1024)
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#define DEFAULT_AGP_APER_SIZE (64*1024*1024)
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/*
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* A small note about bridges and interrupts. The DECchip 21050 (and
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* later) adheres to the PCI-PCI bridge specification. This says that
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* the interrupts on the other side of a bridge are swizzled in the
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* following manner:
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*
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* Dev Interrupt Interrupt
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* Pin on Pin on
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* Device Connector
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*
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* 4 A A
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* B B
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* C C
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* D D
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*
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* 5 A B
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* B C
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* C D
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* D A
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*
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* 6 A C
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* B D
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* C A
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* D B
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*
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* 7 A D
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* B A
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* C B
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* D C
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*
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* Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
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* Thus, each swizzle is ((pin-1) + (device#-4)) % 4
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*
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* pci_swizzle_interrupt_pin() swizzles for exactly one bridge. The routine
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* pci_common_swizzle() handles multiple bridges. But there are a
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* couple boards that do strange things.
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*/
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/* The following macro is used to implement the table-based irq mapping
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function for all single-bus Alphas. */
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#define COMMON_TABLE_LOOKUP \
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({ long _ctl_ = -1; \
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if (slot >= min_idsel && slot <= max_idsel && pin < irqs_per_slot) \
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_ctl_ = irq_tab[slot - min_idsel][pin]; \
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_ctl_; })
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/* A PCI IOMMU allocation arena. There are typically two of these
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regions per bus. */
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/* ??? The 8400 has a 32-byte pte entry, and the entire table apparently
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lives directly on the host bridge (no tlb?). We don't support this
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machine, but if we ever did, we'd need to parameterize all this quite
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a bit further. Probably with per-bus operation tables. */
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struct pci_iommu_arena
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{
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spinlock_t lock;
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struct pci_controller *hose;
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#define IOMMU_INVALID_PTE 0x2 /* 32:63 bits MBZ */
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#define IOMMU_RESERVED_PTE 0xface
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unsigned long *ptes;
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dma_addr_t dma_base;
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unsigned int size;
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unsigned int next_entry;
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unsigned int align_entry;
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};
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#if defined(CONFIG_ALPHA_SRM) && \
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(defined(CONFIG_ALPHA_CIA) || defined(CONFIG_ALPHA_LCA) || \
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defined(CONFIG_ALPHA_AVANTI))
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# define NEED_SRM_SAVE_RESTORE
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#else
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# undef NEED_SRM_SAVE_RESTORE
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#endif
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#if defined(CONFIG_ALPHA_GENERIC) || defined(NEED_SRM_SAVE_RESTORE)
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# define ALPHA_RESTORE_SRM_SETUP
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#else
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# undef ALPHA_RESTORE_SRM_SETUP
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#endif
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#ifdef ALPHA_RESTORE_SRM_SETUP
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extern void pci_restore_srm_config(void);
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#else
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#define pci_restore_srm_config() do {} while (0)
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#endif
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/* The hose list. */
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extern struct pci_controller *hose_head, **hose_tail;
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extern struct pci_controller *pci_isa_hose;
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extern unsigned long alpha_agpgart_size;
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extern void common_init_pci(void);
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#define common_swizzle pci_common_swizzle
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extern struct pci_controller *alloc_pci_controller(void);
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extern struct resource *alloc_resource(void);
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extern struct pci_iommu_arena *iommu_arena_new_node(int,
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struct pci_controller *,
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dma_addr_t, unsigned long,
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unsigned long);
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extern struct pci_iommu_arena *iommu_arena_new(struct pci_controller *,
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dma_addr_t, unsigned long,
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unsigned long);
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extern const char *const pci_io_names[];
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extern const char *const pci_mem_names[];
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extern const char pci_hae0_name[];
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extern unsigned long size_for_memory(unsigned long max);
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extern int iommu_reserve(struct pci_iommu_arena *, long, long);
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extern int iommu_release(struct pci_iommu_arena *, long, long);
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extern int iommu_bind(struct pci_iommu_arena *, long, long, struct page **);
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extern int iommu_unbind(struct pci_iommu_arena *, long, long);
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