164 lines
4 KiB
C
Executable file
164 lines
4 KiB
C
Executable file
// SPDX-License-Identifier: GPL-2.0
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/*
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* linux/arch/alpha/lib/memcpy.c
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*
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* Copyright (C) 1995 Linus Torvalds
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*/
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/*
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* This is a reasonably optimized memcpy() routine.
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*/
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/*
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* Note that the C code is written to be optimized into good assembly. However,
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* at this point gcc is unable to sanely compile "if (n >= 0)", resulting in a
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* explicit compare against 0 (instead of just using the proper "blt reg, xx" or
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* "bge reg, xx"). I hope alpha-gcc will be fixed to notice this eventually..
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*/
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#include <linux/types.h>
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#include <linux/export.h>
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/*
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* This should be done in one go with ldq_u*2/mask/stq_u. Do it
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* with a macro so that we can fix it up later..
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*/
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#define ALIGN_DEST_TO8_UP(d,s,n) \
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while (d & 7) { \
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if (n <= 0) return; \
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n--; \
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*(char *) d = *(char *) s; \
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d++; s++; \
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}
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#define ALIGN_DEST_TO8_DN(d,s,n) \
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while (d & 7) { \
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if (n <= 0) return; \
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n--; \
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d--; s--; \
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*(char *) d = *(char *) s; \
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}
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/*
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* This should similarly be done with ldq_u*2/mask/stq. The destination
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* is aligned, but we don't fill in a full quad-word
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*/
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#define DO_REST_UP(d,s,n) \
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while (n > 0) { \
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n--; \
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*(char *) d = *(char *) s; \
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d++; s++; \
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}
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#define DO_REST_DN(d,s,n) \
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while (n > 0) { \
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n--; \
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d--; s--; \
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*(char *) d = *(char *) s; \
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}
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/*
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* This should be done with ldq/mask/stq. The source and destination are
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* aligned, but we don't fill in a full quad-word
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*/
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#define DO_REST_ALIGNED_UP(d,s,n) DO_REST_UP(d,s,n)
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#define DO_REST_ALIGNED_DN(d,s,n) DO_REST_DN(d,s,n)
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/*
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* This does unaligned memory copies. We want to avoid storing to
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* an unaligned address, as that would do a read-modify-write cycle.
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* We also want to avoid double-reading the unaligned reads.
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*
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* Note the ordering to try to avoid load (and address generation) latencies.
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*/
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static inline void __memcpy_unaligned_up (unsigned long d, unsigned long s,
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long n)
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{
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ALIGN_DEST_TO8_UP(d,s,n);
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n -= 8; /* to avoid compare against 8 in the loop */
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if (n >= 0) {
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unsigned long low_word, high_word;
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__asm__("ldq_u %0,%1":"=r" (low_word):"m" (*(unsigned long *) s));
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do {
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unsigned long tmp;
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__asm__("ldq_u %0,%1":"=r" (high_word):"m" (*(unsigned long *)(s+8)));
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n -= 8;
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__asm__("extql %1,%2,%0"
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:"=r" (low_word)
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:"r" (low_word), "r" (s));
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__asm__("extqh %1,%2,%0"
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:"=r" (tmp)
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:"r" (high_word), "r" (s));
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s += 8;
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*(unsigned long *) d = low_word | tmp;
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d += 8;
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low_word = high_word;
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} while (n >= 0);
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}
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n += 8;
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DO_REST_UP(d,s,n);
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}
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static inline void __memcpy_unaligned_dn (unsigned long d, unsigned long s,
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long n)
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{
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/* I don't understand AXP assembler well enough for this. -Tim */
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s += n;
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d += n;
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while (n--)
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* (char *) --d = * (char *) --s;
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}
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/*
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* Hmm.. Strange. The __asm__ here is there to make gcc use an integer register
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* for the load-store. I don't know why, but it would seem that using a floating
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* point register for the move seems to slow things down (very small difference,
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* though).
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*
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* Note the ordering to try to avoid load (and address generation) latencies.
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*/
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static inline void __memcpy_aligned_up (unsigned long d, unsigned long s,
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long n)
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{
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ALIGN_DEST_TO8_UP(d,s,n);
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n -= 8;
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while (n >= 0) {
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unsigned long tmp;
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__asm__("ldq %0,%1":"=r" (tmp):"m" (*(unsigned long *) s));
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n -= 8;
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s += 8;
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*(unsigned long *) d = tmp;
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d += 8;
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}
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n += 8;
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DO_REST_ALIGNED_UP(d,s,n);
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}
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static inline void __memcpy_aligned_dn (unsigned long d, unsigned long s,
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long n)
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{
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s += n;
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d += n;
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ALIGN_DEST_TO8_DN(d,s,n);
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n -= 8;
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while (n >= 0) {
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unsigned long tmp;
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s -= 8;
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__asm__("ldq %0,%1":"=r" (tmp):"m" (*(unsigned long *) s));
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n -= 8;
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d -= 8;
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*(unsigned long *) d = tmp;
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}
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n += 8;
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DO_REST_ALIGNED_DN(d,s,n);
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}
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void * memcpy(void * dest, const void *src, size_t n)
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{
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if (!(((unsigned long) dest ^ (unsigned long) src) & 7)) {
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__memcpy_aligned_up ((unsigned long) dest, (unsigned long) src,
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n);
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return dest;
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}
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__memcpy_unaligned_up ((unsigned long) dest, (unsigned long) src, n);
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return dest;
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}
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EXPORT_SYMBOL(memcpy);
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