175 lines
4.8 KiB
C
Executable file
175 lines
4.8 KiB
C
Executable file
/*
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* Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <asm/irq.h>
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#define NR_CPU_IRQS 32 /* number of irq lines coming in */
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#define TIMER0_IRQ 3 /* Fixed by ISA */
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/*
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* Early Hardware specific Interrupt setup
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* -Platform independent, needed for each CPU (not foldable into init_IRQ)
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* -Called very early (start_kernel -> setup_arch -> setup_processor)
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*
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* what it does ?
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* -Optionally, setup the High priority Interrupts as Level 2 IRQs
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*/
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void arc_init_IRQ(void)
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{
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unsigned int level_mask = 0, i;
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/* Is timer high priority Interrupt (Level2 in ARCompact jargon) */
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level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;
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/*
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* Write to register, even if no LV2 IRQs configured to reset it
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* in case bootloader had mucked with it
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*/
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write_aux_reg(AUX_IRQ_LEV, level_mask);
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if (level_mask)
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pr_info("Level-2 interrupts bitset %x\n", level_mask);
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/*
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* Disable all IRQ lines so faulty external hardware won't
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* trigger interrupt that kernel is not ready to handle.
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*/
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for (i = TIMER0_IRQ; i < NR_CPU_IRQS; i++) {
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unsigned int ienb;
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ienb = read_aux_reg(AUX_IENABLE);
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ienb &= ~(1 << i);
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write_aux_reg(AUX_IENABLE, ienb);
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}
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}
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/*
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* ARC700 core includes a simple on-chip intc supporting
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* -per IRQ enable/disable
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* -2 levels of interrupts (high/low)
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* -all interrupts being level triggered
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*
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* To reduce platform code, we assume all IRQs directly hooked-up into intc.
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* Platforms with external intc, hence cascaded IRQs, are free to over-ride
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* below, per IRQ.
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*/
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static void arc_irq_mask(struct irq_data *data)
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{
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unsigned int ienb;
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ienb = read_aux_reg(AUX_IENABLE);
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ienb &= ~(1 << data->hwirq);
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write_aux_reg(AUX_IENABLE, ienb);
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}
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static void arc_irq_unmask(struct irq_data *data)
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{
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unsigned int ienb;
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ienb = read_aux_reg(AUX_IENABLE);
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ienb |= (1 << data->hwirq);
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write_aux_reg(AUX_IENABLE, ienb);
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}
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static struct irq_chip onchip_intc = {
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.name = "ARC In-core Intc",
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.irq_mask = arc_irq_mask,
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.irq_unmask = arc_irq_unmask,
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};
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static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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switch (hw) {
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case TIMER0_IRQ:
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irq_set_percpu_devid(irq);
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irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
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break;
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default:
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irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
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}
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return 0;
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}
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static const struct irq_domain_ops arc_intc_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = arc_intc_domain_map,
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};
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static int __init
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init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
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{
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struct irq_domain *root_domain;
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if (parent)
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panic("DeviceTree incore intc not a root irq controller\n");
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root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS,
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&arc_intc_domain_ops, NULL);
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if (!root_domain)
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panic("root irq domain not avail\n");
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/*
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* Needed for primary domain lookup to succeed
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* This is a primary irqchip, and can never have a parent
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*/
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irq_set_default_host(root_domain);
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return 0;
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}
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IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
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/*
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* arch_local_irq_enable - Enable interrupts.
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*
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* 1. Explicitly called to re-enable interrupts
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* 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
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* which maybe in hard ISR itself
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*
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* Semantics of this function change depending on where it is called from:
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*
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* -If called from hard-ISR, it must not invert interrupt priorities
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* e.g. suppose TIMER is high priority (Level 2) IRQ
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* Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
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* Here local_irq_enable( ) shd not re-enable lower priority interrupts
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* -If called from soft-ISR, it must re-enable all interrupts
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* soft ISR are low prioity jobs which can be very slow, thus all IRQs
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* must be enabled while they run.
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* Now hardware context wise we may still be in L2 ISR (not done rtie)
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* still we must re-enable both L1 and L2 IRQs
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* Another twist is prev scenario with flow being
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* L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR
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* here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
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* over-written (this is deficiency in ARC700 Interrupt mechanism)
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*/
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */
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void arch_local_irq_enable(void)
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{
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unsigned long flags = arch_local_save_flags();
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if (flags & STATUS_A2_MASK)
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flags |= STATUS_E2_MASK;
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else if (flags & STATUS_A1_MASK)
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flags |= STATUS_E1_MASK;
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arch_local_irq_restore(flags);
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}
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EXPORT_SYMBOL(arch_local_irq_enable);
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#endif
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