219 lines
5.4 KiB
C
Executable file
219 lines
5.4 KiB
C
Executable file
/*
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* Copyright(c) 2015 EZchip Technologies.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*/
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#ifndef _PLAT_EZNPS_CTOP_H
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#define _PLAT_EZNPS_CTOP_H
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#ifndef CONFIG_ARC_PLAT_EZNPS
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#error "Incorrect ctop.h include"
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#endif
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#include <linux/types.h>
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#include <soc/nps/common.h>
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/* core auxiliary registers */
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#ifdef __ASSEMBLY__
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#define CTOP_AUX_BASE (-0x800)
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#else
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#define CTOP_AUX_BASE 0xFFFFF800
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#endif
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#define CTOP_AUX_GLOBAL_ID (CTOP_AUX_BASE + 0x000)
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#define CTOP_AUX_CLUSTER_ID (CTOP_AUX_BASE + 0x004)
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#define CTOP_AUX_CORE_ID (CTOP_AUX_BASE + 0x008)
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#define CTOP_AUX_THREAD_ID (CTOP_AUX_BASE + 0x00C)
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#define CTOP_AUX_LOGIC_GLOBAL_ID (CTOP_AUX_BASE + 0x010)
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#define CTOP_AUX_LOGIC_CLUSTER_ID (CTOP_AUX_BASE + 0x014)
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#define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018)
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#define CTOP_AUX_MT_CTRL (CTOP_AUX_BASE + 0x020)
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#define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024)
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#define CTOP_AUX_DPC (CTOP_AUX_BASE + 0x02C)
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#define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030)
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#define CTOP_AUX_EFLAGS (CTOP_AUX_BASE + 0x080)
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#define CTOP_AUX_GPA1 (CTOP_AUX_BASE + 0x08C)
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#define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300)
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/* EZchip core instructions */
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#define CTOP_INST_HWSCHD_WFT_IE12 0x3E6F7344
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#define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF
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#define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103
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#define CTOP_INST_SCHD_RW 0x3E6F7004
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#define CTOP_INST_SCHD_RD 0x3E6F7084
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#define CTOP_INST_ASRI_0_R3 0x3B56003E
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#define CTOP_INST_XEX_DI_R2_R2_R3 0x4A664C00
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#define CTOP_INST_EXC_DI_R2_R2_R3 0x4A664C01
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#define CTOP_INST_AADD_DI_R2_R2_R3 0x4A664C02
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#define CTOP_INST_AAND_DI_R2_R2_R3 0x4A664C04
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#define CTOP_INST_AOR_DI_R2_R2_R3 0x4A664C05
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#define CTOP_INST_AXOR_DI_R2_R2_R3 0x4A664C06
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/* Do not use D$ for address in 2G-3G */
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#define HW_COMPLY_KRN_NOT_D_CACHED _BITUL(28)
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#define NPS_MSU_EN_CFG 0x80
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#define NPS_CRG_BLKID 0x480
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#define NPS_CRG_SYNC_BIT _BITUL(0)
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#define NPS_GIM_BLKID 0x5C0
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/* GIM registers and fields*/
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#define NPS_GIM_UART_LINE _BITUL(7)
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#define NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE _BITUL(10)
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#define NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE _BITUL(11)
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#define NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE _BITUL(25)
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#define NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE _BITUL(26)
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#ifndef __ASSEMBLY__
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/* Functional registers definition */
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struct nps_host_reg_mtm_cfg {
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union {
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struct {
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u32 gen:1, gdis:1, clk_gate_dis:1, asb:1,
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__reserved:9, nat:3, ten:16;
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};
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u32 value;
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};
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};
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struct nps_host_reg_mtm_cpu_cfg {
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union {
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struct {
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u32 csa:22, dmsid:6, __reserved:3, cs:1;
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};
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u32 value;
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};
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};
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struct nps_host_reg_thr_init {
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union {
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struct {
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u32 str:1, __reserved:27, thr_id:4;
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};
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u32 value;
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};
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};
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struct nps_host_reg_thr_init_sts {
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union {
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struct {
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u32 bsy:1, err:1, __reserved:26, thr_id:4;
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};
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u32 value;
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};
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};
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struct nps_host_reg_msu_en_cfg {
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union {
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struct {
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u32 __reserved1:11,
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rtc_en:1, ipc_en:1, gim_1_en:1,
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gim_0_en:1, ipi_en:1, buff_e_rls_bmuw:1,
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buff_e_alc_bmuw:1, buff_i_rls_bmuw:1, buff_i_alc_bmuw:1,
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buff_e_rls_bmue:1, buff_e_alc_bmue:1, buff_i_rls_bmue:1,
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buff_i_alc_bmue:1, __reserved2:1, buff_e_pre_en:1,
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buff_i_pre_en:1, pmuw_ja_en:1, pmue_ja_en:1,
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pmuw_nj_en:1, pmue_nj_en:1, msu_en:1;
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};
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u32 value;
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};
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};
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struct nps_host_reg_gim_p_int_dst {
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union {
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struct {
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u32 int_out_en:1, __reserved1:4,
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is:1, intm:2, __reserved2:4,
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nid:4, __reserved3:4, cid:4,
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__reserved4:4, tid:4;
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};
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u32 value;
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};
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};
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/* AUX registers definition */
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struct nps_host_reg_aux_dpc {
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union {
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struct {
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u32 ien:1, men:1, hen:1, reserved:29;
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};
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u32 value;
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};
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};
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struct nps_host_reg_aux_udmc {
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union {
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struct {
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u32 dcp:1, cme:1, __reserved:19, nat:3,
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__reserved2:5, dcas:3;
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};
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u32 value;
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};
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};
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struct nps_host_reg_aux_mt_ctrl {
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union {
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struct {
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u32 mten:1, hsen:1, scd:1, sten:1,
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st_cnt:8, __reserved:8,
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hs_cnt:8, __reserved1:4;
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};
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u32 value;
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};
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};
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struct nps_host_reg_aux_hw_comply {
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union {
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struct {
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u32 me:1, le:1, te:1, knc:1, __reserved:28;
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};
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u32 value;
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};
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};
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struct nps_host_reg_aux_lpc {
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union {
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struct {
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u32 mep:1, __reserved:31;
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};
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u32 value;
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};
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};
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/* CRG registers */
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#define REG_GEN_PURP_0 nps_host_reg_non_cl(NPS_CRG_BLKID, 0x1BF)
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/* GIM registers */
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#define REG_GIM_P_INT_EN_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x100)
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#define REG_GIM_P_INT_POL_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x110)
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#define REG_GIM_P_INT_SENS_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x114)
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#define REG_GIM_P_INT_BLK_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x118)
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#define REG_GIM_P_INT_DST_10 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13A)
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#define REG_GIM_P_INT_DST_11 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13B)
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#define REG_GIM_P_INT_DST_25 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x149)
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#define REG_GIM_P_INT_DST_26 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x14A)
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#else
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.macro GET_CPU_ID reg
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lr \reg, [CTOP_AUX_LOGIC_GLOBAL_ID]
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#ifndef CONFIG_EZNPS_MTM_EXT
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lsr \reg, \reg, 4
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#endif
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* _PLAT_EZNPS_CTOP_H */
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