315 lines
6.8 KiB
Plaintext
Executable file
315 lines
6.8 KiB
Plaintext
Executable file
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2015 Marvell Technology Group Ltd.
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*
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* Author: Jisheng Zhang <jszhang@marvell.com>
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "marvell,berlin4ct", "marvell,berlin";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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cpu-idle-states = <&CPU_SLEEP_0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x1>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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cpu-idle-states = <&CPU_SLEEP_0>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x2>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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cpu-idle-states = <&CPU_SLEEP_0>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x3>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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cpu-idle-states = <&CPU_SLEEP_0>;
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};
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l2: cache {
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compatible = "cache";
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};
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idle-states {
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entry-method = "psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <75>;
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exit-latency-us = <155>;
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min-residency-us = <1000>;
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};
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};
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};
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osc: osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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pmu {
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compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>,
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<&cpu1>,
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<&cpu2>,
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<&cpu3>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc@f7000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0xf7000000 0x1000000>;
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gic: interrupt-controller@901000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x901000 0x1000>,
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<0x902000 0x2000>,
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<0x904000 0x2000>,
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<0x906000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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apb@e80000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xe80000 0x10000>;
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interrupt-parent = <&aic>;
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gpio0: gpio@400 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0400 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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porta: gpio-port@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0>;
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};
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};
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gpio1: gpio@800 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0800 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portb: gpio-port@1 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <1>;
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};
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};
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gpio2: gpio@c00 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0c00 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portc: gpio-port@2 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <2>;
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};
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};
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gpio3: gpio@1000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x1000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portd: gpio-port@3 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <3>;
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};
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};
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aic: interrupt-controller@3800 {
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compatible = "snps,dw-apb-ictl";
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reg = <0x3800 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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soc_pinctrl: pin-controller@ea8000 {
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compatible = "marvell,berlin4ct-soc-pinctrl";
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reg = <0xea8000 0x14>;
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};
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avio_pinctrl: pin-controller@ea8400 {
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compatible = "marvell,berlin4ct-avio-pinctrl";
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reg = <0xea8400 0x8>;
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};
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apb@fc0000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xfc0000 0x10000>;
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interrupt-parent = <&sic>;
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sic: interrupt-controller@1000 {
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compatible = "snps,dw-apb-ictl";
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reg = <0x1000 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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};
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wdt0: watchdog@3000 {
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compatible = "snps,dw-wdt";
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reg = <0x3000 0x100>;
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clocks = <&osc>;
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interrupts = <0>;
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};
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wdt1: watchdog@4000 {
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compatible = "snps,dw-wdt";
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reg = <0x4000 0x100>;
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clocks = <&osc>;
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interrupts = <1>;
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};
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wdt2: watchdog@5000 {
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compatible = "snps,dw-wdt";
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reg = <0x5000 0x100>;
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clocks = <&osc>;
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interrupts = <2>;
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};
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sm_gpio0: gpio@8000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x8000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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porte: gpio-port@4 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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};
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sm_gpio1: gpio@9000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x9000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portf: gpio-port@5 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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};
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uart0: uart@d000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xd000 0x100>;
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interrupts = <8>;
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clocks = <&osc>;
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reg-shift = <2>;
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status = "disabled";
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pinctrl-0 = <&uart0_pmux>;
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pinctrl-names = "default";
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};
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};
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system_pinctrl: pin-controller@fe2200 {
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compatible = "marvell,berlin4ct-system-pinctrl";
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reg = <0xfe2200 0xc>;
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uart0_pmux: uart0-pmux {
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groups = "SM_URT0_TXD", "SM_URT0_RXD";
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function = "uart0";
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};
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};
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};
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};
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