191 lines
5.3 KiB
ArmAsm
Executable file
191 lines
5.3 KiB
ArmAsm
Executable file
/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <asm/alternative.h>
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#include <asm/asm-offsets.h>
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#include <asm/assembler.h>
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#include <asm/fpsimdmacros.h>
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#include <asm/kvm.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_mmu.h>
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#define CPU_GP_REG_OFFSET(x) (CPU_GP_REGS + x)
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#define CPU_XREG_OFFSET(x) CPU_GP_REG_OFFSET(CPU_USER_PT_REGS + 8*x)
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.text
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.pushsection .hyp.text, "ax"
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/*
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* We treat x18 as callee-saved as the host may use it as a platform
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* register (e.g. for shadow call stack).
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*/
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.macro save_callee_saved_regs ctxt
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str x18, [\ctxt, #CPU_XREG_OFFSET(18)]
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stp x19, x20, [\ctxt, #CPU_XREG_OFFSET(19)]
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stp x21, x22, [\ctxt, #CPU_XREG_OFFSET(21)]
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stp x23, x24, [\ctxt, #CPU_XREG_OFFSET(23)]
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stp x25, x26, [\ctxt, #CPU_XREG_OFFSET(25)]
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stp x27, x28, [\ctxt, #CPU_XREG_OFFSET(27)]
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stp x29, lr, [\ctxt, #CPU_XREG_OFFSET(29)]
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.endm
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.macro restore_callee_saved_regs ctxt
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// We require \ctxt is not x18-x28
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ldr x18, [\ctxt, #CPU_XREG_OFFSET(18)]
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ldp x19, x20, [\ctxt, #CPU_XREG_OFFSET(19)]
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ldp x21, x22, [\ctxt, #CPU_XREG_OFFSET(21)]
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ldp x23, x24, [\ctxt, #CPU_XREG_OFFSET(23)]
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ldp x25, x26, [\ctxt, #CPU_XREG_OFFSET(25)]
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ldp x27, x28, [\ctxt, #CPU_XREG_OFFSET(27)]
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ldp x29, lr, [\ctxt, #CPU_XREG_OFFSET(29)]
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.endm
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/*
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* u64 __guest_enter(struct kvm_vcpu *vcpu,
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* struct kvm_cpu_context *host_ctxt);
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*/
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ENTRY(__guest_enter)
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// x0: vcpu
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// x1: host context
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// x2-x17: clobbered by macros
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// x29: guest context
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// Store the host regs
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save_callee_saved_regs x1
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// Now the host state is stored if we have a pending RAS SError it must
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// affect the host. If any asynchronous exception is pending we defer
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// the guest entry. The DSB isn't necessary before v8.2 as any SError
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// would be fatal.
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alternative_if ARM64_HAS_RAS_EXTN
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dsb nshst
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isb
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alternative_else_nop_endif
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mrs x1, isr_el1
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cbz x1, 1f
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mov x0, #ARM_EXCEPTION_IRQ
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ret
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1:
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add x29, x0, #VCPU_CONTEXT
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// Restore guest regs x0-x17
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ldp x0, x1, [x29, #CPU_XREG_OFFSET(0)]
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ldp x2, x3, [x29, #CPU_XREG_OFFSET(2)]
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ldp x4, x5, [x29, #CPU_XREG_OFFSET(4)]
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ldp x6, x7, [x29, #CPU_XREG_OFFSET(6)]
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ldp x8, x9, [x29, #CPU_XREG_OFFSET(8)]
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ldp x10, x11, [x29, #CPU_XREG_OFFSET(10)]
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ldp x12, x13, [x29, #CPU_XREG_OFFSET(12)]
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ldp x14, x15, [x29, #CPU_XREG_OFFSET(14)]
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ldp x16, x17, [x29, #CPU_XREG_OFFSET(16)]
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// Restore guest regs x18-x29, lr
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restore_callee_saved_regs x29
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// Do not touch any register after this!
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eret
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ENDPROC(__guest_enter)
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ENTRY(__guest_exit)
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// x0: return code
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// x1: vcpu
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// x2-x29,lr: vcpu regs
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// vcpu x0-x1 on the stack
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add x1, x1, #VCPU_CONTEXT
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ALTERNATIVE(nop, SET_PSTATE_PAN(1), ARM64_HAS_PAN, CONFIG_ARM64_PAN)
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// Store the guest regs x2 and x3
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stp x2, x3, [x1, #CPU_XREG_OFFSET(2)]
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// Retrieve the guest regs x0-x1 from the stack
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ldp x2, x3, [sp], #16 // x0, x1
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// Store the guest regs x0-x1 and x4-x17
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stp x2, x3, [x1, #CPU_XREG_OFFSET(0)]
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stp x4, x5, [x1, #CPU_XREG_OFFSET(4)]
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stp x6, x7, [x1, #CPU_XREG_OFFSET(6)]
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stp x8, x9, [x1, #CPU_XREG_OFFSET(8)]
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stp x10, x11, [x1, #CPU_XREG_OFFSET(10)]
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stp x12, x13, [x1, #CPU_XREG_OFFSET(12)]
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stp x14, x15, [x1, #CPU_XREG_OFFSET(14)]
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stp x16, x17, [x1, #CPU_XREG_OFFSET(16)]
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// Store the guest regs x18-x29, lr
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save_callee_saved_regs x1
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get_host_ctxt x2, x3
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// Now restore the host regs
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restore_callee_saved_regs x2
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alternative_if ARM64_HAS_RAS_EXTN
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// If we have the RAS extensions we can consume a pending error
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// without an unmask-SError and isb.
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esb
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mrs_s x2, SYS_DISR_EL1
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str x2, [x1, #(VCPU_FAULT_DISR - VCPU_CONTEXT)]
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cbz x2, 1f
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msr_s SYS_DISR_EL1, xzr
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orr x0, x0, #(1<<ARM_EXIT_WITH_SERROR_BIT)
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1: ret
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alternative_else
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// If we have a pending asynchronous abort, now is the
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// time to find out. From your VAXorcist book, page 666:
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// "Threaten me not, oh Evil one! For I speak with
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// the power of DEC, and I command thee to show thyself!"
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mrs x2, elr_el2
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mrs x3, esr_el2
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mrs x4, spsr_el2
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mov x5, x0
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dsb sy // Synchronize against in-flight ld/st
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nop
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msr daifclr, #4 // Unmask aborts
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alternative_endif
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// This is our single instruction exception window. A pending
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// SError is guaranteed to occur at the earliest when we unmask
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// it, and at the latest just after the ISB.
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abort_guest_exit_start:
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isb
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abort_guest_exit_end:
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msr daifset, #4 // Mask aborts
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ret
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_kvm_extable abort_guest_exit_start, 9997f
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_kvm_extable abort_guest_exit_end, 9997f
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9997:
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msr daifset, #4 // Mask aborts
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mov x0, #(1 << ARM_EXIT_WITH_SERROR_BIT)
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// restore the EL1 exception context so that we can report some
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// information. Merge the exception code with the SError pending bit.
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msr elr_el2, x2
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msr esr_el2, x3
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msr spsr_el2, x4
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orr x0, x0, x5
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1: ret
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ENDPROC(__guest_exit)
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