148 lines
2.7 KiB
Plaintext
Executable file
148 lines
2.7 KiB
Plaintext
Executable file
// SPDX-License-Identifier: GPL-2.0
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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model = "ti,c66x";
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};
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cpu@1 {
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device_type = "cpu";
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reg = <1>;
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model = "ti,c66x";
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};
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cpu@2 {
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device_type = "cpu";
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reg = <2>;
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model = "ti,c66x";
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};
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cpu@3 {
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device_type = "cpu";
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reg = <3>;
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model = "ti,c66x";
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};
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cpu@4 {
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device_type = "cpu";
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reg = <4>;
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model = "ti,c66x";
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};
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cpu@5 {
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device_type = "cpu";
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reg = <5>;
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model = "ti,c66x";
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};
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cpu@6 {
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device_type = "cpu";
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reg = <6>;
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model = "ti,c66x";
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};
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cpu@7 {
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device_type = "cpu";
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reg = <7>;
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model = "ti,c66x";
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};
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};
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soc {
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compatible = "simple-bus";
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model = "tms320c6678";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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core_pic: interrupt-controller {
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compatible = "ti,c64x+core-pic";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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megamod_pic: interrupt-controller@1800000 {
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compatible = "ti,c64x+megamod-pic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1800000 0x1000>;
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interrupt-parent = <&core_pic>;
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};
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cache-controller@1840000 {
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compatible = "ti,c64x+cache";
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reg = <0x01840000 0x8400>;
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};
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timer8: timer@2280000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x01 >;
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reg = <0x2280000 0x40>;
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};
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timer9: timer@2290000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x02 >;
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reg = <0x2290000 0x40>;
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};
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timer10: timer@22A0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x04 >;
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reg = <0x22A0000 0x40>;
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};
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timer11: timer@22B0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x08 >;
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reg = <0x22B0000 0x40>;
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};
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timer12: timer@22C0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x10 >;
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reg = <0x22C0000 0x40>;
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};
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timer13: timer@22D0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x20 >;
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reg = <0x22D0000 0x40>;
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};
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timer14: timer@22E0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x40 >;
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reg = <0x22E0000 0x40>;
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};
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timer15: timer@22F0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x80 >;
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reg = <0x22F0000 0x40>;
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};
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clock-controller@2310000 {
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compatible = "ti,c6678-pll", "ti,c64x+pll";
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reg = <0x02310000 0x200>;
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ti,c64x+pll-bypass-delay = <200>;
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ti,c64x+pll-reset-delay = <12000>;
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ti,c64x+pll-lock-delay = <80000>;
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};
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device-state-controller@2620000 {
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compatible = "ti,c64x+dscr";
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reg = <0x02620000 0x1000>;
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ti,dscr-devstat = <0x20>;
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ti,dscr-silicon-rev = <0x18 28 0xf>;
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ti,dscr-mac-fuse-regs = <0x110 1 2 3 4
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0x114 5 6 0 0>;
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};
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};
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};
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