260 lines
6.3 KiB
C
Executable file
260 lines
6.3 KiB
C
Executable file
/*
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* pci.c -- PCI bus support for ColdFire processors
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*
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* (C) Copyright 2012, Greg Ungerer <gerg@uclinux.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/m54xxpci.h>
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/*
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* Memory and IO mappings. We use a 1:1 mapping for local host memory to
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* PCI bus memory (no reason not to really). IO space is mapped in its own
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* separate address region. The device configuration space is mapped over
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* the IO map space when we enable it in the PCICAR register.
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*/
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static struct pci_bus *rootbus;
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static unsigned long iospace;
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/*
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* We need to be carefull probing on bus 0 (directly connected to host
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* bridge). We should only access the well defined possible devices in
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* use, ignore aliases and the like.
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*/
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static unsigned char mcf_host_slot2sid[32] = {
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 2, 0, 3, 4, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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};
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static unsigned char mcf_host_irq[] = {
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0, 69, 69, 71, 71,
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};
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/*
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* Configuration space access functions. Configuration space access is
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* through the IO mapping window, enabling it via the PCICAR register.
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*/
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static unsigned long mcf_mk_pcicar(int bus, unsigned int devfn, int where)
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{
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return (bus << PCICAR_BUSN) | (devfn << PCICAR_DEVFNN) | (where & 0xfc);
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}
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static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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unsigned long addr;
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*value = 0xffffffff;
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if (bus->number == 0) {
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if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
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return PCIBIOS_SUCCESSFUL;
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}
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addr = mcf_mk_pcicar(bus->number, devfn, where);
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__raw_writel(PCICAR_E | addr, PCICAR);
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__raw_readl(PCICAR);
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addr = iospace + (where & 0x3);
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switch (size) {
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case 1:
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*value = __raw_readb(addr);
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break;
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case 2:
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*value = le16_to_cpu(__raw_readw(addr));
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break;
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default:
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*value = le32_to_cpu(__raw_readl(addr));
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break;
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}
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__raw_writel(0, PCICAR);
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__raw_readl(PCICAR);
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return PCIBIOS_SUCCESSFUL;
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}
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static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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unsigned long addr;
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if (bus->number == 0) {
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if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
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return PCIBIOS_SUCCESSFUL;
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}
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addr = mcf_mk_pcicar(bus->number, devfn, where);
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__raw_writel(PCICAR_E | addr, PCICAR);
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__raw_readl(PCICAR);
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addr = iospace + (where & 0x3);
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switch (size) {
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case 1:
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__raw_writeb(value, addr);
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break;
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case 2:
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__raw_writew(cpu_to_le16(value), addr);
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break;
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default:
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__raw_writel(cpu_to_le32(value), addr);
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break;
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}
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__raw_writel(0, PCICAR);
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__raw_readl(PCICAR);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops mcf_pci_ops = {
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.read = mcf_pci_readconfig,
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.write = mcf_pci_writeconfig,
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};
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/*
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* Initialize the PCI bus registers, and scan the bus.
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*/
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static struct resource mcf_pci_mem = {
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.name = "PCI Memory space",
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.start = PCI_MEM_PA,
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.end = PCI_MEM_PA + PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct resource mcf_pci_io = {
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.name = "PCI IO space",
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.start = 0x400,
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.end = 0x10000 - 1,
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.flags = IORESOURCE_IO,
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};
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static struct resource busn_resource = {
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.name = "PCI busn",
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.start = 0,
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.end = 255,
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.flags = IORESOURCE_BUS,
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};
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/*
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* Interrupt mapping and setting.
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*/
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static int mcf_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int sid;
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sid = mcf_host_slot2sid[slot];
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if (sid)
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return mcf_host_irq[sid];
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return 0;
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}
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static int __init mcf_pci_init(void)
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{
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struct pci_host_bridge *bridge;
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int ret;
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bridge = pci_alloc_host_bridge(0);
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if (!bridge)
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return -ENOMEM;
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pr_info("ColdFire: PCI bus initialization...\n");
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/* Reset the external PCI bus */
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__raw_writel(PCIGSCR_RESET, PCIGSCR);
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__raw_writel(0, PCITCR);
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request_resource(&iomem_resource, &mcf_pci_mem);
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request_resource(&iomem_resource, &mcf_pci_io);
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/* Configure PCI arbiter */
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__raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
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PACR_EXTMINTE(0x1f), PACR);
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/* Set required multi-function pins for PCI bus use */
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__raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
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__raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
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/* Set up config space for local host bus controller */
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__raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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PCI_COMMAND_INVALIDATE, PCISCR);
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__raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
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__raw_writel(0, PCICR2);
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/*
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* Set up the initiator windows for memory and IO mapping.
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* These give the CPU bus access onto the PCI bus. One for each of
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* PCI memory and IO address spaces.
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*/
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__raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
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PCIIW0BTAR);
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__raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
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PCIIW1BTAR);
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__raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
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PCIIWCR_W1_IO | PCIIWCR_W1_E, PCIIWCR);
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/*
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* Set up the target windows for access from the PCI bus back to the
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* CPU bus. All we need is access to system RAM (for mastering).
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*/
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__raw_writel(CONFIG_RAMBASE, PCIBAR1);
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__raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
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/* Keep a virtual mapping to IO/config space active */
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iospace = (unsigned long) ioremap(PCI_IO_PA, PCI_IO_SIZE);
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if (iospace == 0) {
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pci_free_host_bridge(bridge);
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return -ENODEV;
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}
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pr_info("Coldfire: PCI IO/config window mapped to 0x%x\n",
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(u32) iospace);
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/* Turn of PCI reset, and wait for devices to settle */
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__raw_writel(0, PCIGSCR);
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set_current_state(TASK_UNINTERRUPTIBLE);
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schedule_timeout(msecs_to_jiffies(200));
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pci_add_resource(&bridge->windows, &ioport_resource);
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pci_add_resource(&bridge->windows, &iomem_resource);
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pci_add_resource(&bridge->windows, &busn_resource);
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bridge->dev.parent = NULL;
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bridge->sysdata = NULL;
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bridge->busnr = 0;
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bridge->ops = &mcf_pci_ops;
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bridge->swizzle_irq = pci_common_swizzle;
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bridge->map_irq = mcf_pci_map_irq;
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ret = pci_scan_root_bus_bridge(bridge);
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if (ret) {
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pci_free_host_bridge(bridge);
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return ret;
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}
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rootbus = bridge->bus;
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rootbus->resource[0] = &mcf_pci_io;
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rootbus->resource[1] = &mcf_pci_mem;
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pci_bus_size_bridges(rootbus);
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pci_bus_assign_resources(rootbus);
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pci_bus_add_devices(rootbus);
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return 0;
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}
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subsys_initcall(mcf_pci_init);
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