120 lines
2.7 KiB
C
Executable file
120 lines
2.7 KiB
C
Executable file
/*
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* stmark2.c -- Support for Sysam AMCORE open board
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*
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* (C) Copyright 2017, Angelo Dureghello <angelo@sysam.it>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/mtd/partitions.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-fsl-dspi.h>
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#include <linux/spi/flash.h>
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#include <asm/mcfsim.h>
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/*
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* Partitioning of parallel NOR flash (39VF3201B)
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*/
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static struct mtd_partition stmark2_partitions[] = {
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{
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.name = "U-Boot (1024K)",
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.size = 0x100000,
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.offset = 0x0
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}, {
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.name = "Kernel+initramfs (7168K)",
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.size = 0x700000,
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.offset = MTDPART_OFS_APPEND
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}, {
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.name = "Flash Free Space (8192K)",
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.size = MTDPART_SIZ_FULL,
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.offset = MTDPART_OFS_APPEND
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}
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};
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static struct flash_platform_data stmark2_spi_flash_data = {
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.name = "is25lp128",
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.parts = stmark2_partitions,
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.nr_parts = ARRAY_SIZE(stmark2_partitions),
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.type = "is25lp128",
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};
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static struct spi_board_info stmark2_board_info[] __initdata = {
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{
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.modalias = "m25p80",
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.max_speed_hz = 5000000,
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.bus_num = 0,
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.chip_select = 1,
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.platform_data = &stmark2_spi_flash_data,
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.mode = SPI_MODE_3,
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}
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};
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/* SPI controller data, SPI (0) */
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static struct fsl_dspi_platform_data dspi_spi0_info = {
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.cs_num = 4,
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.bus_num = 0,
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.sck_cs_delay = 100,
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.cs_sck_delay = 100,
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};
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static struct resource dspi_spi0_resource[] = {
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[0] = {
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.start = MCFDSPI_BASE0,
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.end = MCFDSPI_BASE0 + 0xFF,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 12,
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.end = 13,
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.flags = IORESOURCE_DMA,
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},
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[2] = {
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.start = MCF_IRQ_DSPI0,
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.end = MCF_IRQ_DSPI0,
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.flags = IORESOURCE_IRQ,
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},
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};
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/* SPI controller, id = bus number */
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static struct platform_device dspi_spi0_device = {
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.name = "fsl-dspi",
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.id = 0,
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.num_resources = ARRAY_SIZE(dspi_spi0_resource),
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.resource = dspi_spi0_resource,
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.dev = {
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.platform_data = &dspi_spi0_info,
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},
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};
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static struct platform_device *stmark2_devices[] __initdata = {
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&dspi_spi0_device,
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};
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/*
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* Note: proper pin-mux setup is mandatory for proper SPI functionality.
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*/
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static int __init init_stmark2(void)
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{
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/* DSPI0, all pins as DSPI, and using CS1 */
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__raw_writeb(0x80, MCFGPIO_PAR_DSPIOWL);
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__raw_writeb(0xfc, MCFGPIO_PAR_DSPIOWH);
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/* Board gpio setup */
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__raw_writeb(0x00, MCFGPIO_PAR_BE);
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__raw_writeb(0x00, MCFGPIO_PAR_FBCTL);
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__raw_writeb(0x00, MCFGPIO_PAR_CS);
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__raw_writeb(0x00, MCFGPIO_PAR_CANI2C);
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platform_add_devices(stmark2_devices, ARRAY_SIZE(stmark2_devices));
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spi_register_board_info(stmark2_board_info,
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ARRAY_SIZE(stmark2_board_info));
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return 0;
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}
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late_initcall(init_stmark2);
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