121 lines
4.6 KiB
Plaintext
Executable file
121 lines
4.6 KiB
Plaintext
Executable file
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
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M68000 Hi-Performance Microprocessor Division
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M68060 Software Package
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Production Release P1.00 -- October 10, 1994
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M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
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THE SOFTWARE is provided on an "AS IS" basis and without warranty.
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To the maximum extent permitted by applicable law,
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MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
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INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
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and any warranty against infringement with regard to the SOFTWARE
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(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
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To the maximum extent permitted by applicable law,
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IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
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(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
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BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
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ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
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Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
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You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
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so long as this entire notice is retained without alteration in any modified and/or
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redistributed versions, and that such modified versions are clearly identified as such.
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No licenses are granted by implication, estoppel or otherwise under any patents
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or trademarks of Motorola, Inc.
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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CHANGES SINCE LAST RELEASE:
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---------------------------
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1) "movep" emulation where data was being read from memory
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was reading the intermediate bytes. Emulation now only
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reads the required bytes.
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2) "flogn", "flog2", and "flog10" of "1" was setting the
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Inexact FPSR bit. Emulation now does not set Inexact for
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this case.
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3) For an opclass three FP instruction where the effective addressing
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mode was pre-decrement or post-increment and the address register
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was A0 or A1, the address register was not being updated as a result
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of the operation. This has been corrected.
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4) Beta B.2 version had the following erratum:
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Scenario:
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---------
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If {i,d}mem_{read,write}_{byte,word,long}() returns
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a failing value to the 68060SP, the package ignores
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this return value and continues with program execution
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as if it never received a failing value.
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Effect:
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-------
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For example, if a user executed "fsin.x ADDR,fp0" where
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ADDR should cause a "segmentation violation", the memory read
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requested by the package should return a failing value
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to the package. Since the package currently ignores this
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return value, the user program will continue to the
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next instruction, and the result created in fp0 will be
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undefined.
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Fix:
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----
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This has been fixed in the current release.
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Notes:
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------
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Upon receiving a non-zero (failing) return value from
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a {i,d}mem_{read,write}_{byte,word,long}() "call-out",
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the package creates a 16-byte access error stack frame
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from the current exception stack frame and exits
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through the "call-out" _real_access(). This is the process
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as described in the MC68060 User's Manual.
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For instruction read access errors, the info stacked is:
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SR = SR at time of exception
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PC = PC of instruction being emulated
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VOFF = $4008 (stack frame format type)
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ADDRESS = PC of instruction being emulated
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FSLW = FAULT STATUS LONGWORD
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The valid FSLW bits are:
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bit 27 = 1 (misaligned bit)
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bit 24 = 1 (read)
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bit 23 = 0 (write)
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bit 22:21 = 10 (SIZE = word)
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bit 20:19 = 00 (TT)
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bit 18:16 = x10 (TM; x = 1 for supervisor mode)
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bit 15 = 1 (IO)
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bit 0 = 1 (Software Emulation Error)
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all other bits are EQUAL TO ZERO and can be set by the _real_access()
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"call-out" stub by the user as appropriate. The MC68060 User's Manual
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stated that ONLY "bit 0" would be set. The 060SP attempts to set a few
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other bits.
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For data read/write access errors, the info stacked is:
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SR = SR at time of exception
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PC = PC of instruction being emulated
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VOFF = $4008 (stack frame format type)
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ADDRESS = Address of source or destination operand
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FSLW = FAULT STATUS LONGWORD
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The valid FSLW bits are:
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bit 27 = 0 (misaligned bit)
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bit 24 = x (read; 1 if read, 0 if write)
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bit 23 = x (write; 1 if write, 0 if read)
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bit 22:21 = xx (SIZE; see MC68060 User's Manual)
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bit 20:19 = 00 (TT)
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bit 18:16 = x01 (TM; x = 1 for supervisor mode)
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bit 15 = 0 (IO)
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bit 0 = 1 (Software Emulation Error)
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all other bits are EQUAL TO ZERO and can be set by the _real_access()
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"call-out" stub by the user as appropriate. The MC68060 User's Manual
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stated that ONLY "bit 0" would be set. The 060SP attempts to set a few
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other bits.
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