266 lines
7.9 KiB
C
Executable file
266 lines
7.9 KiB
C
Executable file
/*
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*
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* BRIEF MODULE DESCRIPTION
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* A DMA channel allocator for Au1x00. API is modeled loosely off of
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* linux/kernel/dma.c.
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*
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* Copyright 2000, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1000_dma.h>
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/*
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* A note on resource allocation:
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*
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* All drivers needing DMA channels, should allocate and release them
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* through the public routines `request_dma()' and `free_dma()'.
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*
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* In order to avoid problems, all processes should allocate resources in
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* the same sequence and release them in the reverse order.
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*
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* So, when allocating DMAs and IRQs, first allocate the DMA, then the IRQ.
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* When releasing them, first release the IRQ, then release the DMA. The
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* main reason for this order is that, if you are requesting the DMA buffer
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* done interrupt, you won't know the irq number until the DMA channel is
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* returned from request_dma.
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*/
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/* DMA Channel register block spacing */
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#define DMA_CHANNEL_LEN 0x00000100
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DEFINE_SPINLOCK(au1000_dma_spin_lock);
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struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = {
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{.dev_id = -1,},
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{.dev_id = -1,},
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{.dev_id = -1,},
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{.dev_id = -1,},
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{.dev_id = -1,},
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{.dev_id = -1,},
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{.dev_id = -1,},
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{.dev_id = -1,}
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};
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EXPORT_SYMBOL(au1000_dma_table);
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/* Device FIFO addresses and default DMA modes */
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static const struct dma_dev {
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unsigned int fifo_addr;
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unsigned int dma_mode;
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} dma_dev_table[DMA_NUM_DEV] = {
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{ AU1000_UART0_PHYS_ADDR + 0x04, DMA_DW8 }, /* UART0_TX */
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{ AU1000_UART0_PHYS_ADDR + 0x00, DMA_DW8 | DMA_DR }, /* UART0_RX */
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{ 0, 0 }, /* DMA_REQ0 */
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{ 0, 0 }, /* DMA_REQ1 */
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{ AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 }, /* AC97 TX c */
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{ AU1000_AC97_PHYS_ADDR + 0x08, DMA_DW16 | DMA_DR }, /* AC97 RX c */
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{ AU1000_UART3_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* UART3_TX */
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{ AU1000_UART3_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* UART3_RX */
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{ AU1000_USB_UDC_PHYS_ADDR + 0x00, DMA_DW8 | DMA_NC | DMA_DR }, /* EP0RD */
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{ AU1000_USB_UDC_PHYS_ADDR + 0x04, DMA_DW8 | DMA_NC }, /* EP0WR */
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{ AU1000_USB_UDC_PHYS_ADDR + 0x08, DMA_DW8 | DMA_NC }, /* EP2WR */
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{ AU1000_USB_UDC_PHYS_ADDR + 0x0c, DMA_DW8 | DMA_NC }, /* EP3WR */
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{ AU1000_USB_UDC_PHYS_ADDR + 0x10, DMA_DW8 | DMA_NC | DMA_DR }, /* EP4RD */
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{ AU1000_USB_UDC_PHYS_ADDR + 0x14, DMA_DW8 | DMA_NC | DMA_DR }, /* EP5RD */
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/* on Au1500, these 2 are DMA_REQ2/3 (GPIO208/209) instead! */
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{ AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC}, /* I2S TX */
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{ AU1000_I2S_PHYS_ADDR + 0x00, DMA_DW32 | DMA_NC | DMA_DR}, /* I2S RX */
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};
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int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
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int length, int *eof, void *data)
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{
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int i, len = 0;
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struct dma_chan *chan;
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for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
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chan = get_dma_chan(i);
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if (chan != NULL)
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len += sprintf(buf + len, "%2d: %s\n",
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i, chan->dev_str);
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}
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if (fpos >= len) {
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*start = buf;
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*eof = 1;
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return 0;
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}
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*start = buf + fpos;
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len -= fpos;
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if (len > length)
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return length;
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*eof = 1;
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return len;
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}
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/* Device FIFO addresses and default DMA modes - 2nd bank */
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static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = {
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{ AU1100_SD0_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 }, /* coherent */
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{ AU1100_SD0_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR }, /* coherent */
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{ AU1100_SD1_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 }, /* coherent */
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{ AU1100_SD1_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR } /* coherent */
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};
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void dump_au1000_dma_channel(unsigned int dmanr)
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{
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struct dma_chan *chan;
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if (dmanr >= NUM_AU1000_DMA_CHANNELS)
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return;
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chan = &au1000_dma_table[dmanr];
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printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
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printk(KERN_INFO " mode = 0x%08x\n",
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__raw_readl(chan->io + DMA_MODE_SET));
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printk(KERN_INFO " addr = 0x%08x\n",
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__raw_readl(chan->io + DMA_PERIPHERAL_ADDR));
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printk(KERN_INFO " start0 = 0x%08x\n",
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__raw_readl(chan->io + DMA_BUFFER0_START));
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printk(KERN_INFO " start1 = 0x%08x\n",
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__raw_readl(chan->io + DMA_BUFFER1_START));
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printk(KERN_INFO " count0 = 0x%08x\n",
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__raw_readl(chan->io + DMA_BUFFER0_COUNT));
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printk(KERN_INFO " count1 = 0x%08x\n",
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__raw_readl(chan->io + DMA_BUFFER1_COUNT));
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}
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/*
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* Finds a free channel, and binds the requested device to it.
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* Returns the allocated channel number, or negative on error.
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* Requests the DMA done IRQ if irqhandler != NULL.
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*/
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int request_au1000_dma(int dev_id, const char *dev_str,
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irq_handler_t irqhandler,
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unsigned long irqflags,
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void *irq_dev_id)
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{
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struct dma_chan *chan;
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const struct dma_dev *dev;
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int i, ret;
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if (alchemy_get_cputype() == ALCHEMY_CPU_AU1100) {
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if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
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return -EINVAL;
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} else {
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if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
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return -EINVAL;
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}
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for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
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if (au1000_dma_table[i].dev_id < 0)
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break;
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if (i == NUM_AU1000_DMA_CHANNELS)
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return -ENODEV;
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chan = &au1000_dma_table[i];
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if (dev_id >= DMA_NUM_DEV) {
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dev_id -= DMA_NUM_DEV;
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dev = &dma_dev_table_bank2[dev_id];
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} else
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dev = &dma_dev_table[dev_id];
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if (irqhandler) {
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chan->irq_dev = irq_dev_id;
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ret = request_irq(chan->irq, irqhandler, irqflags, dev_str,
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chan->irq_dev);
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if (ret) {
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chan->irq_dev = NULL;
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return ret;
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}
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} else {
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chan->irq_dev = NULL;
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}
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/* fill it in */
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chan->io = (void __iomem *)(KSEG1ADDR(AU1000_DMA_PHYS_ADDR) +
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i * DMA_CHANNEL_LEN);
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chan->dev_id = dev_id;
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chan->dev_str = dev_str;
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chan->fifo_addr = dev->fifo_addr;
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chan->mode = dev->dma_mode;
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/* initialize the channel before returning */
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init_dma(i);
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return i;
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}
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EXPORT_SYMBOL(request_au1000_dma);
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void free_au1000_dma(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan) {
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printk(KERN_ERR "Error trying to free DMA%d\n", dmanr);
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return;
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}
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disable_dma(dmanr);
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if (chan->irq_dev)
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free_irq(chan->irq, chan->irq_dev);
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chan->irq_dev = NULL;
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chan->dev_id = -1;
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}
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EXPORT_SYMBOL(free_au1000_dma);
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static int __init au1000_dma_init(void)
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{
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int base, i;
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switch (alchemy_get_cputype()) {
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case ALCHEMY_CPU_AU1000:
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base = AU1000_DMA_INT_BASE;
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break;
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case ALCHEMY_CPU_AU1500:
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base = AU1500_DMA_INT_BASE;
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break;
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case ALCHEMY_CPU_AU1100:
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base = AU1100_DMA_INT_BASE;
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break;
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default:
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goto out;
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}
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for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
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au1000_dma_table[i].irq = base + i;
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printk(KERN_INFO "Alchemy DMA initialized\n");
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out:
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return 0;
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}
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arch_initcall(au1000_dma_init);
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