243 lines
6 KiB
C
Executable file
243 lines
6 KiB
C
Executable file
/*
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* Atheros AR7XXX/AR9XXX USB Host Controller device
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/usb/ehci_pdriver.h>
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#include <linux/usb/ohci_pdriver.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "dev-usb.h"
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static u64 ath79_usb_dmamask = DMA_BIT_MASK(32);
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static struct usb_ohci_pdata ath79_ohci_pdata = {
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};
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static struct usb_ehci_pdata ath79_ehci_pdata_v1 = {
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.has_synopsys_hc_bug = 1,
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};
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static struct usb_ehci_pdata ath79_ehci_pdata_v2 = {
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.caps_offset = 0x100,
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.has_tt = 1,
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};
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static void __init ath79_usb_register(const char *name, int id,
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unsigned long base, unsigned long size,
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int irq, const void *data,
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size_t data_size)
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{
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struct resource res[2];
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struct platform_device *pdev;
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memset(res, 0, sizeof(res));
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res[0].flags = IORESOURCE_MEM;
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res[0].start = base;
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res[0].end = base + size - 1;
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res[1].flags = IORESOURCE_IRQ;
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res[1].start = irq;
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res[1].end = irq;
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pdev = platform_device_register_resndata(NULL, name, id,
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res, ARRAY_SIZE(res),
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data, data_size);
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if (IS_ERR(pdev)) {
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pr_err("ath79: unable to register USB at %08lx, err=%d\n",
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base, (int) PTR_ERR(pdev));
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return;
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}
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pdev->dev.dma_mask = &ath79_usb_dmamask;
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pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
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}
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#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
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AR71XX_RESET_USB_PHY | \
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AR71XX_RESET_USB_OHCI_DLL)
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static void __init ath79_usb_setup(void)
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{
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void __iomem *usb_ctrl_base;
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ath79_device_reset_set(AR71XX_USB_RESET_MASK);
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mdelay(1000);
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ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
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usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
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/* Turning on the Buff and Desc swap bits */
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__raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
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/* WAR for HW bug. Here it adjusts the duration between two SOFS */
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__raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
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iounmap(usb_ctrl_base);
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mdelay(900);
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ath79_usb_register("ohci-platform", -1,
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AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE,
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ATH79_MISC_IRQ(6),
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&ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
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ath79_usb_register("ehci-platform", -1,
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AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE,
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ATH79_CPU_IRQ(3),
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&ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1));
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}
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static void __init ar7240_usb_setup(void)
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{
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void __iomem *usb_ctrl_base;
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ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
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ath79_device_reset_set(AR7240_RESET_USB_HOST);
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mdelay(1000);
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ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
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ath79_device_reset_clear(AR7240_RESET_USB_HOST);
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usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
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/* WAR for HW bug. Here it adjusts the duration between two SOFS */
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__raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
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iounmap(usb_ctrl_base);
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ath79_usb_register("ohci-platform", -1,
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AR7240_OHCI_BASE, AR7240_OHCI_SIZE,
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ATH79_CPU_IRQ(3),
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&ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
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}
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static void __init ar724x_usb_setup(void)
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{
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ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
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mdelay(10);
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ath79_device_reset_clear(AR724X_RESET_USB_HOST);
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mdelay(10);
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ath79_device_reset_clear(AR724X_RESET_USB_PHY);
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mdelay(10);
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ath79_usb_register("ehci-platform", -1,
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AR724X_EHCI_BASE, AR724X_EHCI_SIZE,
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ATH79_CPU_IRQ(3),
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&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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}
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static void __init ar913x_usb_setup(void)
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{
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ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
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mdelay(10);
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ath79_device_reset_clear(AR913X_RESET_USB_HOST);
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mdelay(10);
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ath79_device_reset_clear(AR913X_RESET_USB_PHY);
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mdelay(10);
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ath79_usb_register("ehci-platform", -1,
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AR913X_EHCI_BASE, AR913X_EHCI_SIZE,
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ATH79_CPU_IRQ(3),
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&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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}
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static void __init ar933x_usb_setup(void)
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{
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ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
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mdelay(10);
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ath79_device_reset_clear(AR933X_RESET_USB_HOST);
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mdelay(10);
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ath79_device_reset_clear(AR933X_RESET_USB_PHY);
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mdelay(10);
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ath79_usb_register("ehci-platform", -1,
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AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
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ATH79_CPU_IRQ(3),
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&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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}
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static void __init ar934x_usb_setup(void)
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{
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u32 bootstrap;
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bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
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if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
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return;
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ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
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udelay(1000);
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ath79_device_reset_clear(AR934X_RESET_USB_PHY);
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udelay(1000);
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ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG);
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udelay(1000);
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ath79_device_reset_clear(AR934X_RESET_USB_HOST);
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udelay(1000);
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ath79_usb_register("ehci-platform", -1,
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AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
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ATH79_CPU_IRQ(3),
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&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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}
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static void __init qca955x_usb_setup(void)
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{
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ath79_usb_register("ehci-platform", 0,
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QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
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ATH79_IP3_IRQ(0),
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&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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ath79_usb_register("ehci-platform", 1,
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QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
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ATH79_IP3_IRQ(1),
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&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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}
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void __init ath79_register_usb(void)
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{
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if (soc_is_ar71xx())
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ath79_usb_setup();
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else if (soc_is_ar7240())
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ar7240_usb_setup();
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else if (soc_is_ar7241() || soc_is_ar7242())
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ar724x_usb_setup();
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else if (soc_is_ar913x())
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ar913x_usb_setup();
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else if (soc_is_ar933x())
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ar933x_usb_setup();
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else if (soc_is_ar934x())
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ar934x_usb_setup();
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else if (soc_is_qca955x())
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qca955x_usb_setup();
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else
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BUG();
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}
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