184 lines
5.8 KiB
C
Executable file
184 lines
5.8 KiB
C
Executable file
/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __MIPS_ASM_MIPS_CPS_H__
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# error Please include asm/mips-cps.h rather than asm/mips-cpc.h
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#endif
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#ifndef __MIPS_ASM_MIPS_CPC_H__
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#define __MIPS_ASM_MIPS_CPC_H__
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#include <linux/bitops.h>
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#include <linux/errno.h>
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/* The base address of the CPC registers */
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extern void __iomem *mips_cpc_base;
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/**
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* mips_cpc_default_phys_base - retrieve the default physical base address of
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* the CPC
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*
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* Returns the default physical base address of the Cluster Power Controller
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* memory mapped registers. This is platform dependant & must therefore be
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* implemented per-platform.
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*/
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extern phys_addr_t mips_cpc_default_phys_base(void);
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/**
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* mips_cpc_probe - probe for a Cluster Power Controller
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*
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* Attempt to detect the presence of a Cluster Power Controller. Returns 0 if
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* a CPC is successfully detected, else -errno.
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*/
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#ifdef CONFIG_MIPS_CPC
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extern int mips_cpc_probe(void);
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#else
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static inline int mips_cpc_probe(void)
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{
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return -ENODEV;
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}
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#endif
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/**
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* mips_cpc_present - determine whether a Cluster Power Controller is present
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*
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* Returns true if a CPC is present in the system, else false.
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*/
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static inline bool mips_cpc_present(void)
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{
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#ifdef CONFIG_MIPS_CPC
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return mips_cpc_base != NULL;
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#else
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return false;
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#endif
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}
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/* Offsets from the CPC base address to various control blocks */
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#define MIPS_CPC_GCB_OFS 0x0000
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#define MIPS_CPC_CLCB_OFS 0x2000
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#define MIPS_CPC_COCB_OFS 0x4000
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#define CPC_ACCESSOR_RO(sz, off, name) \
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CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_GCB_OFS + off, name) \
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CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
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#define CPC_ACCESSOR_RW(sz, off, name) \
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CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_GCB_OFS + off, name) \
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CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
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#define CPC_CX_ACCESSOR_RO(sz, off, name) \
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CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name) \
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CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
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#define CPC_CX_ACCESSOR_RW(sz, off, name) \
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CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name) \
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CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
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/* CPC_ACCESS - Control core/IOCU access to CPC registers prior to CM 3 */
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CPC_ACCESSOR_RW(32, 0x000, access)
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/* CPC_SEQDEL - Configure delays between command sequencer steps */
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CPC_ACCESSOR_RW(32, 0x008, seqdel)
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/* CPC_RAIL - Configure the delay from rail power-up to stability */
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CPC_ACCESSOR_RW(32, 0x010, rail)
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/* CPC_RESETLEN - Configure the length of reset sequences */
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CPC_ACCESSOR_RW(32, 0x018, resetlen)
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/* CPC_REVISION - Indicates the revisison of the CPC */
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CPC_ACCESSOR_RO(32, 0x020, revision)
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/* CPC_PWRUP_CTL - Control power to the Coherence Manager (CM) */
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CPC_ACCESSOR_RW(32, 0x030, pwrup_ctl)
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#define CPC_PWRUP_CTL_CM_PWRUP BIT(0)
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/* CPC_CONFIG - Mirrors GCR_CONFIG */
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CPC_ACCESSOR_RW(64, 0x138, config)
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/* CPC_SYS_CONFIG - Control cluster endianness */
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CPC_ACCESSOR_RW(32, 0x140, sys_config)
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#define CPC_SYS_CONFIG_BE_IMMEDIATE BIT(2)
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#define CPC_SYS_CONFIG_BE_STATUS BIT(1)
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#define CPC_SYS_CONFIG_BE BIT(0)
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/* CPC_Cx_CMD - Instruct the CPC to take action on a core */
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CPC_CX_ACCESSOR_RW(32, 0x000, cmd)
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#define CPC_Cx_CMD GENMASK(3, 0)
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#define CPC_Cx_CMD_CLOCKOFF 0x1
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#define CPC_Cx_CMD_PWRDOWN 0x2
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#define CPC_Cx_CMD_PWRUP 0x3
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#define CPC_Cx_CMD_RESET 0x4
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/* CPC_Cx_STAT_CONF - Indicates core configuration & state */
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CPC_CX_ACCESSOR_RW(32, 0x008, stat_conf)
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#define CPC_Cx_STAT_CONF_PWRUPE BIT(23)
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#define CPC_Cx_STAT_CONF_SEQSTATE GENMASK(22, 19)
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#define CPC_Cx_STAT_CONF_SEQSTATE_D0 0x0
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#define CPC_Cx_STAT_CONF_SEQSTATE_U0 0x1
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#define CPC_Cx_STAT_CONF_SEQSTATE_U1 0x2
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#define CPC_Cx_STAT_CONF_SEQSTATE_U2 0x3
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#define CPC_Cx_STAT_CONF_SEQSTATE_U3 0x4
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#define CPC_Cx_STAT_CONF_SEQSTATE_U4 0x5
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#define CPC_Cx_STAT_CONF_SEQSTATE_U5 0x6
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#define CPC_Cx_STAT_CONF_SEQSTATE_U6 0x7
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#define CPC_Cx_STAT_CONF_SEQSTATE_D1 0x8
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#define CPC_Cx_STAT_CONF_SEQSTATE_D3 0x9
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#define CPC_Cx_STAT_CONF_SEQSTATE_D2 0xa
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#define CPC_Cx_STAT_CONF_CLKGAT_IMPL BIT(17)
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#define CPC_Cx_STAT_CONF_PWRDN_IMPL BIT(16)
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#define CPC_Cx_STAT_CONF_EJTAG_PROBE BIT(15)
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/* CPC_Cx_OTHER - Configure the core-other register block prior to CM 3 */
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CPC_CX_ACCESSOR_RW(32, 0x010, other)
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#define CPC_Cx_OTHER_CORENUM GENMASK(23, 16)
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/* CPC_Cx_VP_STOP - Stop Virtual Processors (VPs) within a core from running */
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CPC_CX_ACCESSOR_RW(32, 0x020, vp_stop)
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/* CPC_Cx_VP_START - Start Virtual Processors (VPs) within a core running */
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CPC_CX_ACCESSOR_RW(32, 0x028, vp_run)
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/* CPC_Cx_VP_RUNNING - Indicate which Virtual Processors (VPs) are running */
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CPC_CX_ACCESSOR_RW(32, 0x030, vp_running)
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/* CPC_Cx_CONFIG - Mirrors GCR_Cx_CONFIG */
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CPC_CX_ACCESSOR_RW(32, 0x090, config)
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#ifdef CONFIG_MIPS_CPC
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/**
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* mips_cpc_lock_other - lock access to another core
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* core: the other core to be accessed
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*
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* Call before operating upon a core via the 'other' register region in
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* order to prevent the region being moved during access. Must be called
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* within the bounds of a mips_cm_{lock,unlock}_other pair, and followed
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* by a call to mips_cpc_unlock_other.
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*/
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extern void mips_cpc_lock_other(unsigned int core);
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/**
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* mips_cpc_unlock_other - unlock access to another core
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*
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* Call after operating upon another core via the 'other' register region.
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* Must be called after mips_cpc_lock_other.
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*/
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extern void mips_cpc_unlock_other(void);
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#else /* !CONFIG_MIPS_CPC */
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static inline void mips_cpc_lock_other(unsigned int core) { }
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static inline void mips_cpc_unlock_other(void) { }
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#endif /* !CONFIG_MIPS_CPC */
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#endif /* __MIPS_ASM_MIPS_CPC_H__ */
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