525 lines
16 KiB
C
Executable file
525 lines
16 KiB
C
Executable file
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/*
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* Interface to the hardware Packet Input Processing unit.
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*
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*/
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#ifndef __CVMX_PIP_H__
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#define __CVMX_PIP_H__
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#include <asm/octeon/cvmx-wqe.h>
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#include <asm/octeon/cvmx-fpa.h>
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#include <asm/octeon/cvmx-pip-defs.h>
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#define CVMX_PIP_NUM_INPUT_PORTS 48
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#define CVMX_PIP_NUM_WATCHERS 4
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/*
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* Encodes the different error and exception codes
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*/
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typedef enum {
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CVMX_PIP_L4_NO_ERR = 0ull,
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/*
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* 1 = TCP (UDP) packet not long enough to cover TCP (UDP)
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* header
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*/
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CVMX_PIP_L4_MAL_ERR = 1ull,
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/* 2 = TCP/UDP checksum failure */
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CVMX_PIP_CHK_ERR = 2ull,
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/*
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* 3 = TCP/UDP length check (TCP/UDP length does not match IP
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* length).
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*/
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CVMX_PIP_L4_LENGTH_ERR = 3ull,
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/* 4 = illegal TCP/UDP port (either source or dest port is zero) */
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CVMX_PIP_BAD_PRT_ERR = 4ull,
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/* 8 = TCP flags = FIN only */
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CVMX_PIP_TCP_FLG8_ERR = 8ull,
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/* 9 = TCP flags = 0 */
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CVMX_PIP_TCP_FLG9_ERR = 9ull,
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/* 10 = TCP flags = FIN+RST+* */
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CVMX_PIP_TCP_FLG10_ERR = 10ull,
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/* 11 = TCP flags = SYN+URG+* */
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CVMX_PIP_TCP_FLG11_ERR = 11ull,
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/* 12 = TCP flags = SYN+RST+* */
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CVMX_PIP_TCP_FLG12_ERR = 12ull,
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/* 13 = TCP flags = SYN+FIN+* */
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CVMX_PIP_TCP_FLG13_ERR = 13ull
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} cvmx_pip_l4_err_t;
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typedef enum {
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CVMX_PIP_IP_NO_ERR = 0ull,
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/* 1 = not IPv4 or IPv6 */
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CVMX_PIP_NOT_IP = 1ull,
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/* 2 = IPv4 header checksum violation */
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CVMX_PIP_IPV4_HDR_CHK = 2ull,
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/* 3 = malformed (packet not long enough to cover IP hdr) */
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CVMX_PIP_IP_MAL_HDR = 3ull,
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/* 4 = malformed (packet not long enough to cover len in IP hdr) */
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CVMX_PIP_IP_MAL_PKT = 4ull,
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/* 5 = TTL / hop count equal zero */
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CVMX_PIP_TTL_HOP = 5ull,
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/* 6 = IPv4 options / IPv6 early extension headers */
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CVMX_PIP_OPTS = 6ull
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} cvmx_pip_ip_exc_t;
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/**
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* NOTES
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* late collision (data received before collision)
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* late collisions cannot be detected by the receiver
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* they would appear as JAM bits which would appear as bad FCS
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* or carrier extend error which is CVMX_PIP_EXTEND_ERR
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*/
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typedef enum {
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/* No error */
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CVMX_PIP_RX_NO_ERR = 0ull,
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/* RGM+SPI 1 = partially received packet (buffering/bandwidth
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* not adequate) */
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CVMX_PIP_PARTIAL_ERR = 1ull,
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/* RGM+SPI 2 = receive packet too large and truncated */
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CVMX_PIP_JABBER_ERR = 2ull,
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/*
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* RGM 3 = max frame error (pkt len > max frame len) (with FCS
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* error)
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*/
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CVMX_PIP_OVER_FCS_ERR = 3ull,
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/* RGM+SPI 4 = max frame error (pkt len > max frame len) */
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CVMX_PIP_OVER_ERR = 4ull,
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/*
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* RGM 5 = nibble error (data not byte multiple - 100M and 10M
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* only)
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*/
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CVMX_PIP_ALIGN_ERR = 5ull,
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/*
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* RGM 6 = min frame error (pkt len < min frame len) (with FCS
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* error)
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*/
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CVMX_PIP_UNDER_FCS_ERR = 6ull,
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/* RGM 7 = FCS error */
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CVMX_PIP_GMX_FCS_ERR = 7ull,
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/* RGM+SPI 8 = min frame error (pkt len < min frame len) */
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CVMX_PIP_UNDER_ERR = 8ull,
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/* RGM 9 = Frame carrier extend error */
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CVMX_PIP_EXTEND_ERR = 9ull,
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/*
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* RGM 10 = length mismatch (len did not match len in L2
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* length/type)
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*/
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CVMX_PIP_LENGTH_ERR = 10ull,
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/* RGM 11 = Frame error (some or all data bits marked err) */
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CVMX_PIP_DAT_ERR = 11ull,
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/* SPI 11 = DIP4 error */
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CVMX_PIP_DIP_ERR = 11ull,
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/*
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* RGM 12 = packet was not large enough to pass the skipper -
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* no inspection could occur.
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*/
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CVMX_PIP_SKIP_ERR = 12ull,
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/*
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* RGM 13 = studder error (data not repeated - 100M and 10M
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* only)
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*/
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CVMX_PIP_NIBBLE_ERR = 13ull,
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/* RGM+SPI 16 = FCS error */
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CVMX_PIP_PIP_FCS = 16L,
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/*
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* RGM+SPI+PCI 17 = packet was not large enough to pass the
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* skipper - no inspection could occur.
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*/
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CVMX_PIP_PIP_SKIP_ERR = 17L,
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/*
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* RGM+SPI+PCI 18 = malformed l2 (packet not long enough to
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* cover L2 hdr).
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*/
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CVMX_PIP_PIP_L2_MAL_HDR = 18L
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/*
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* NOTES: xx = late collision (data received before collision)
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* late collisions cannot be detected by the receiver
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* they would appear as JAM bits which would appear as
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* bad FCS or carrier extend error which is
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* CVMX_PIP_EXTEND_ERR
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*/
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} cvmx_pip_rcv_err_t;
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/**
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* This defines the err_code field errors in the work Q entry
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*/
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typedef union {
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cvmx_pip_l4_err_t l4_err;
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cvmx_pip_ip_exc_t ip_exc;
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cvmx_pip_rcv_err_t rcv_err;
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} cvmx_pip_err_t;
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/**
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* Status statistics for a port
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*/
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typedef struct {
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/* Inbound octets marked to be dropped by the IPD */
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uint32_t dropped_octets;
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/* Inbound packets marked to be dropped by the IPD */
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uint32_t dropped_packets;
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/* RAW PCI Packets received by PIP per port */
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uint32_t pci_raw_packets;
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/* Number of octets processed by PIP */
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uint32_t octets;
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/* Number of packets processed by PIP */
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uint32_t packets;
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/*
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* Number of identified L2 multicast packets. Does not
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* include broadcast packets. Only includes packets whose
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* parse mode is SKIP_TO_L2
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*/
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uint32_t multicast_packets;
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/*
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* Number of identified L2 broadcast packets. Does not
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* include multicast packets. Only includes packets whose
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* parse mode is SKIP_TO_L2
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*/
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uint32_t broadcast_packets;
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/* Number of 64B packets */
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uint32_t len_64_packets;
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/* Number of 65-127B packets */
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uint32_t len_65_127_packets;
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/* Number of 128-255B packets */
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uint32_t len_128_255_packets;
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/* Number of 256-511B packets */
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uint32_t len_256_511_packets;
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/* Number of 512-1023B packets */
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uint32_t len_512_1023_packets;
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/* Number of 1024-1518B packets */
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uint32_t len_1024_1518_packets;
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/* Number of 1519-max packets */
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uint32_t len_1519_max_packets;
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/* Number of packets with FCS or Align opcode errors */
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uint32_t fcs_align_err_packets;
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/* Number of packets with length < min */
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uint32_t runt_packets;
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/* Number of packets with length < min and FCS error */
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uint32_t runt_crc_packets;
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/* Number of packets with length > max */
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uint32_t oversize_packets;
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/* Number of packets with length > max and FCS error */
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uint32_t oversize_crc_packets;
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/* Number of packets without GMX/SPX/PCI errors received by PIP */
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uint32_t inb_packets;
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/*
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* Total number of octets from all packets received by PIP,
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* including CRC
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*/
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uint64_t inb_octets;
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/* Number of packets with GMX/SPX/PCI errors received by PIP */
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uint16_t inb_errors;
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} cvmx_pip_port_status_t;
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/**
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* Definition of the PIP custom header that can be prepended
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* to a packet by external hardware.
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*/
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typedef union {
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uint64_t u64;
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struct {
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/*
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* Documented as R - Set if the Packet is RAWFULL. If
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* set, this header must be the full 8 bytes.
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*/
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uint64_t rawfull:1;
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/* Must be zero */
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uint64_t reserved0:5;
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/* PIP parse mode for this packet */
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uint64_t parse_mode:2;
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/* Must be zero */
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uint64_t reserved1:1;
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/*
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* Skip amount, including this header, to the
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* beginning of the packet
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*/
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uint64_t skip_len:7;
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/* Must be zero */
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uint64_t reserved2:6;
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/* POW input queue for this packet */
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uint64_t qos:3;
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/* POW input group for this packet */
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uint64_t grp:4;
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/*
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* Flag to store this packet in the work queue entry,
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* if possible
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*/
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uint64_t rs:1;
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/* POW input tag type */
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uint64_t tag_type:2;
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/* POW input tag */
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uint64_t tag:32;
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} s;
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} cvmx_pip_pkt_inst_hdr_t;
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/* CSR typedefs have been moved to cvmx-csr-*.h */
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/**
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* Configure an ethernet input port
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*
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* @port_num: Port number to configure
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* @port_cfg: Port hardware configuration
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* @port_tag_cfg:
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* Port POW tagging configuration
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*/
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static inline void cvmx_pip_config_port(uint64_t port_num,
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union cvmx_pip_prt_cfgx port_cfg,
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union cvmx_pip_prt_tagx port_tag_cfg)
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{
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cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
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cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
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}
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#if 0
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/**
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* @deprecated This function is a thin wrapper around the Pass1 version
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* of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for
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* setting the group that is incompatible with this function,
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* the preferred upgrade path is to use the CSR directly.
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*
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* Configure the global QoS packet watchers. Each watcher is
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* capable of matching a field in a packet to determine the
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* QoS queue for scheduling.
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*
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* @watcher: Watcher number to configure (0 - 3).
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* @match_type: Watcher match type
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* @match_value:
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* Value the watcher will match against
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* @qos: QoS queue for packets matching this watcher
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*/
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static inline void cvmx_pip_config_watcher(uint64_t watcher,
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cvmx_pip_qos_watch_types match_type,
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uint64_t match_value, uint64_t qos)
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{
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cvmx_pip_port_watcher_cfg_t watcher_config;
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watcher_config.u64 = 0;
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watcher_config.s.match_type = match_type;
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watcher_config.s.match_value = match_value;
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watcher_config.s.qos = qos;
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cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
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}
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#endif
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/**
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* Configure the VLAN priority to QoS queue mapping.
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*
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* @vlan_priority:
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* VLAN priority (0-7)
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* @qos: QoS queue for packets matching this watcher
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*/
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static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority,
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uint64_t qos)
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{
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union cvmx_pip_qos_vlanx pip_qos_vlanx;
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pip_qos_vlanx.u64 = 0;
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pip_qos_vlanx.s.qos = qos;
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cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);
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}
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/**
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* Configure the Diffserv to QoS queue mapping.
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*
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* @diffserv: Diffserv field value (0-63)
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* @qos: QoS queue for packets matching this watcher
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*/
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static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos)
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{
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union cvmx_pip_qos_diffx pip_qos_diffx;
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pip_qos_diffx.u64 = 0;
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pip_qos_diffx.s.qos = qos;
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cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);
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}
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/**
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* Get the status counters for a port.
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*
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* @port_num: Port number to get statistics for.
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* @clear: Set to 1 to clear the counters after they are read
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* @status: Where to put the results.
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*/
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static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear,
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cvmx_pip_port_status_t *status)
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{
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union cvmx_pip_stat_ctl pip_stat_ctl;
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union cvmx_pip_stat0_prtx stat0;
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union cvmx_pip_stat1_prtx stat1;
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union cvmx_pip_stat2_prtx stat2;
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union cvmx_pip_stat3_prtx stat3;
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union cvmx_pip_stat4_prtx stat4;
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union cvmx_pip_stat5_prtx stat5;
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union cvmx_pip_stat6_prtx stat6;
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union cvmx_pip_stat7_prtx stat7;
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union cvmx_pip_stat8_prtx stat8;
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union cvmx_pip_stat9_prtx stat9;
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union cvmx_pip_stat_inb_pktsx pip_stat_inb_pktsx;
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union cvmx_pip_stat_inb_octsx pip_stat_inb_octsx;
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union cvmx_pip_stat_inb_errsx pip_stat_inb_errsx;
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pip_stat_ctl.u64 = 0;
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pip_stat_ctl.s.rdclr = clear;
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cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
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stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
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stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
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stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
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stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
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stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
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stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
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stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
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stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
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stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
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stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
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pip_stat_inb_pktsx.u64 =
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cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
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pip_stat_inb_octsx.u64 =
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cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
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pip_stat_inb_errsx.u64 =
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cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
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status->dropped_octets = stat0.s.drp_octs;
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status->dropped_packets = stat0.s.drp_pkts;
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status->octets = stat1.s.octs;
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status->pci_raw_packets = stat2.s.raw;
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status->packets = stat2.s.pkts;
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status->multicast_packets = stat3.s.mcst;
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status->broadcast_packets = stat3.s.bcst;
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status->len_64_packets = stat4.s.h64;
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status->len_65_127_packets = stat4.s.h65to127;
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status->len_128_255_packets = stat5.s.h128to255;
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status->len_256_511_packets = stat5.s.h256to511;
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status->len_512_1023_packets = stat6.s.h512to1023;
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status->len_1024_1518_packets = stat6.s.h1024to1518;
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status->len_1519_max_packets = stat7.s.h1519;
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status->fcs_align_err_packets = stat7.s.fcs;
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status->runt_packets = stat8.s.undersz;
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status->runt_crc_packets = stat8.s.frag;
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status->oversize_packets = stat9.s.oversz;
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status->oversize_crc_packets = stat9.s.jabber;
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status->inb_packets = pip_stat_inb_pktsx.s.pkts;
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status->inb_octets = pip_stat_inb_octsx.s.octs;
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status->inb_errors = pip_stat_inb_errsx.s.errs;
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if (cvmx_octeon_is_pass1()) {
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/*
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* Kludge to fix Octeon Pass 1 errata - Drop counts
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* don't work.
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*/
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if (status->inb_packets > status->packets)
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status->dropped_packets =
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status->inb_packets - status->packets;
|
|
else
|
|
status->dropped_packets = 0;
|
|
if (status->inb_octets - status->inb_packets * 4 >
|
|
status->octets)
|
|
status->dropped_octets =
|
|
status->inb_octets - status->inb_packets * 4 -
|
|
status->octets;
|
|
else
|
|
status->dropped_octets = 0;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Configure the hardware CRC engine
|
|
*
|
|
* @interface: Interface to configure (0 or 1)
|
|
* @invert_result:
|
|
* Invert the result of the CRC
|
|
* @reflect: Reflect
|
|
* @initialization_vector:
|
|
* CRC initialization vector
|
|
*/
|
|
static inline void cvmx_pip_config_crc(uint64_t interface,
|
|
uint64_t invert_result, uint64_t reflect,
|
|
uint32_t initialization_vector)
|
|
{
|
|
if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
|
|
union cvmx_pip_crc_ctlx config;
|
|
union cvmx_pip_crc_ivx pip_crc_ivx;
|
|
|
|
config.u64 = 0;
|
|
config.s.invres = invert_result;
|
|
config.s.reflect = reflect;
|
|
cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64);
|
|
|
|
pip_crc_ivx.u64 = 0;
|
|
pip_crc_ivx.s.iv = initialization_vector;
|
|
cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Clear all bits in a tag mask. This should be called on
|
|
* startup before any calls to cvmx_pip_tag_mask_set. Each bit
|
|
* set in the final mask represent a byte used in the packet for
|
|
* tag generation.
|
|
*
|
|
* @mask_index: Which tag mask to clear (0..3)
|
|
*/
|
|
static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index)
|
|
{
|
|
uint64_t index;
|
|
union cvmx_pip_tag_incx pip_tag_incx;
|
|
pip_tag_incx.u64 = 0;
|
|
pip_tag_incx.s.en = 0;
|
|
for (index = mask_index * 16; index < (mask_index + 1) * 16; index++)
|
|
cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
|
|
}
|
|
|
|
/**
|
|
* Sets a range of bits in the tag mask. The tag mask is used
|
|
* when the cvmx_pip_port_tag_cfg_t tag_mode is non zero.
|
|
* There are four separate masks that can be configured.
|
|
*
|
|
* @mask_index: Which tag mask to modify (0..3)
|
|
* @offset: Offset into the bitmask to set bits at. Use the GCC macro
|
|
* offsetof() to determine the offsets into packet headers.
|
|
* For example, offsetof(ethhdr, protocol) returns the offset
|
|
* of the ethernet protocol field. The bitmask selects which
|
|
* bytes to include the the tag, with bit offset X selecting
|
|
* byte at offset X from the beginning of the packet data.
|
|
* @len: Number of bytes to include. Usually this is the sizeof()
|
|
* the field.
|
|
*/
|
|
static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset,
|
|
uint64_t len)
|
|
{
|
|
while (len--) {
|
|
union cvmx_pip_tag_incx pip_tag_incx;
|
|
uint64_t index = mask_index * 16 + offset / 8;
|
|
pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index));
|
|
pip_tag_incx.s.en |= 0x80 >> (offset & 0x7);
|
|
cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
|
|
offset++;
|
|
}
|
|
}
|
|
|
|
#endif /* __CVMX_PIP_H__ */
|