210 lines
6.5 KiB
C
Executable file
210 lines
6.5 KiB
C
Executable file
/*
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* Copyright (c) 2003-2014 Broadcom Corporation
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* All Rights Reserved
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/bitops.h>
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#include <asm/cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/mips-extns.h>
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#define SATA_CTL 0x0
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#define SATA_STATUS 0x1 /* Status Reg */
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#define SATA_INT 0x2 /* Interrupt Reg */
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#define SATA_INT_MASK 0x3 /* Interrupt Mask Reg */
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#define SATA_CR_REG_TIMER 0x4 /* PHY Conrol Timer Reg */
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#define SATA_CORE_ID 0x5 /* Core ID Reg */
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#define SATA_AXI_SLAVE_OPT1 0x6 /* AXI Slave Options Reg */
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#define SATA_PHY_LOS_LEV 0x7 /* PHY LOS Level Reg */
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#define SATA_PHY_MULTI 0x8 /* PHY Multiplier Reg */
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#define SATA_PHY_CLK_SEL 0x9 /* Clock Select Reg */
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#define SATA_PHY_AMP1_GEN1 0xa /* PHY Transmit Amplitude Reg 1 */
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#define SATA_PHY_AMP1_GEN2 0xb /* PHY Transmit Amplitude Reg 2 */
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#define SATA_PHY_AMP1_GEN3 0xc /* PHY Transmit Amplitude Reg 3 */
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#define SATA_PHY_PRE1 0xd /* PHY Transmit Preemphasis Reg 1 */
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#define SATA_PHY_PRE2 0xe /* PHY Transmit Preemphasis Reg 2 */
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#define SATA_PHY_PRE3 0xf /* PHY Transmit Preemphasis Reg 3 */
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#define SATA_SPDMODE 0x10 /* Speed Mode Reg */
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#define SATA_REFCLK 0x11 /* Reference Clock Control Reg */
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#define SATA_BYTE_SWAP_DIS 0x12 /* byte swap disable */
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/*SATA_CTL Bits */
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#define SATA_RST_N BIT(0)
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#define PHY0_RESET_N BIT(16)
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#define PHY1_RESET_N BIT(17)
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#define PHY2_RESET_N BIT(18)
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#define PHY3_RESET_N BIT(19)
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#define M_CSYSREQ BIT(2)
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#define S_CSYSREQ BIT(3)
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/*SATA_STATUS Bits */
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#define P0_PHY_READY BIT(4)
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#define P1_PHY_READY BIT(5)
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#define P2_PHY_READY BIT(6)
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#define P3_PHY_READY BIT(7)
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#define nlm_read_sata_reg(b, r) nlm_read_reg(b, r)
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#define nlm_write_sata_reg(b, r, v) nlm_write_reg(b, r, v)
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#define nlm_get_sata_pcibase(node) \
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nlm_pcicfg_base(XLP_IO_SATA_OFFSET(node))
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/* SATA device specific configuration registers are starts at 0x900 offset */
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#define nlm_get_sata_regbase(node) \
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(nlm_get_sata_pcibase(node) + 0x900)
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static void sata_clear_glue_reg(uint64_t regbase, uint32_t off, uint32_t bit)
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{
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uint32_t reg_val;
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reg_val = nlm_read_sata_reg(regbase, off);
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nlm_write_sata_reg(regbase, off, (reg_val & ~bit));
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}
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static void sata_set_glue_reg(uint64_t regbase, uint32_t off, uint32_t bit)
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{
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uint32_t reg_val;
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reg_val = nlm_read_sata_reg(regbase, off);
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nlm_write_sata_reg(regbase, off, (reg_val | bit));
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}
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static void nlm_sata_firmware_init(int node)
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{
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uint32_t reg_val;
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uint64_t regbase;
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int i;
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pr_info("XLP AHCI Initialization started.\n");
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regbase = nlm_get_sata_regbase(node);
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/* Reset SATA */
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sata_clear_glue_reg(regbase, SATA_CTL, SATA_RST_N);
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/* Reset PHY */
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sata_clear_glue_reg(regbase, SATA_CTL,
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(PHY3_RESET_N | PHY2_RESET_N
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| PHY1_RESET_N | PHY0_RESET_N));
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/* Set SATA */
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sata_set_glue_reg(regbase, SATA_CTL, SATA_RST_N);
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/* Set PHY */
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sata_set_glue_reg(regbase, SATA_CTL,
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(PHY3_RESET_N | PHY2_RESET_N
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| PHY1_RESET_N | PHY0_RESET_N));
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pr_debug("Waiting for PHYs to come up.\n");
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i = 0;
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do {
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reg_val = nlm_read_sata_reg(regbase, SATA_STATUS);
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i++;
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} while (((reg_val & 0xF0) != 0xF0) && (i < 10000));
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for (i = 0; i < 4; i++) {
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if (reg_val & (P0_PHY_READY << i))
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pr_info("PHY%d is up.\n", i);
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else
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pr_info("PHY%d is down.\n", i);
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}
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pr_info("XLP AHCI init done.\n");
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}
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static int __init nlm_ahci_init(void)
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{
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int node = 0;
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int chip = read_c0_prid() & PRID_IMP_MASK;
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if (chip == PRID_IMP_NETLOGIC_XLP3XX)
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nlm_sata_firmware_init(node);
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return 0;
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}
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static void nlm_sata_intr_ack(struct irq_data *data)
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{
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uint32_t val = 0;
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uint64_t regbase;
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regbase = nlm_get_sata_regbase(nlm_nodeid());
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val = nlm_read_sata_reg(regbase, SATA_INT);
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sata_set_glue_reg(regbase, SATA_INT, val);
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}
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static void nlm_sata_fixup_bar(struct pci_dev *dev)
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{
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/*
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* The AHCI resource is in BAR 0, move it to
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* BAR 5, where it is expected
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*/
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dev->resource[5] = dev->resource[0];
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memset(&dev->resource[0], 0, sizeof(dev->resource[0]));
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}
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static void nlm_sata_fixup_final(struct pci_dev *dev)
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{
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uint32_t val;
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uint64_t regbase;
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int node = 0; /* XLP3XX does not support multi-node */
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regbase = nlm_get_sata_regbase(node);
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/* clear pending interrupts and then enable them */
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val = nlm_read_sata_reg(regbase, SATA_INT);
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sata_set_glue_reg(regbase, SATA_INT, val);
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/* Mask the core interrupt. If all the interrupts
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* are enabled there are spurious interrupt flow
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* happening, to avoid only enable core interrupt
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* mask.
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*/
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sata_set_glue_reg(regbase, SATA_INT_MASK, 0x1);
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dev->irq = PIC_SATA_IRQ;
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nlm_set_pic_extra_ack(node, PIC_SATA_IRQ, nlm_sata_intr_ack);
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}
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arch_initcall(nlm_ahci_init);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_SATA,
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nlm_sata_fixup_bar);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_SATA,
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nlm_sata_fixup_final);
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