433 lines
12 KiB
C
Executable file
433 lines
12 KiB
C
Executable file
/*
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* linux/arch/mips/txx9/pci.c
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*
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* Based on linux/arch/mips/txx9/rbtx4927/setup.c,
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* linux/arch/mips/txx9/rbtx4938/setup.c,
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* and RBTX49xx patch from CELF patch archive.
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*
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* Copyright 2001-2005 MontaVista Software Inc.
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* Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
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* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/delay.h>
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#include <linux/jiffies.h>
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#include <linux/io.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/pci.h>
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#ifdef CONFIG_TOSHIBA_FPCIB0
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <asm/i8259.h>
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#include <asm/txx9/smsc_fdc37m81x.h>
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#endif
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static int __init
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early_read_config_word(struct pci_controller *hose,
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int top_bus, int bus, int devfn, int offset, u16 *value)
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{
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struct pci_bus fake_bus;
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fake_bus.number = bus;
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fake_bus.sysdata = hose;
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fake_bus.ops = hose->pci_ops;
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if (bus != top_bus)
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/* Fake a parent bus structure. */
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fake_bus.parent = &fake_bus;
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else
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fake_bus.parent = NULL;
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return pci_bus_read_config_word(&fake_bus, devfn, offset, value);
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}
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int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
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int current_bus)
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{
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u32 pci_devfn;
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unsigned short vid;
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int cap66 = -1;
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u16 stat;
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/* It seems SLC90E66 needs some time after PCI reset... */
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mdelay(80);
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pr_info("PCI: Checking 66MHz capabilities...\n");
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for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
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if (PCI_FUNC(pci_devfn))
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continue;
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if (early_read_config_word(hose, top_bus, current_bus,
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pci_devfn, PCI_VENDOR_ID, &vid) !=
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PCIBIOS_SUCCESSFUL)
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continue;
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if (vid == 0xffff)
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continue;
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/* check 66MHz capability */
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if (cap66 < 0)
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cap66 = 1;
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if (cap66) {
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early_read_config_word(hose, top_bus, current_bus,
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pci_devfn, PCI_STATUS, &stat);
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if (!(stat & PCI_STATUS_66MHZ)) {
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pr_debug("PCI: %02x:%02x not 66MHz capable.\n",
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current_bus, pci_devfn);
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cap66 = 0;
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break;
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}
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}
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}
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return cap66 > 0;
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}
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static struct resource primary_pci_mem_res[2] = {
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{ .name = "PCI MEM" },
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{ .name = "PCI MMIO" },
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};
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static struct resource primary_pci_io_res = { .name = "PCI IO" };
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struct pci_controller txx9_primary_pcic = {
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.mem_resource = &primary_pci_mem_res[0],
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.io_resource = &primary_pci_io_res,
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};
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#ifdef CONFIG_64BIT
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int txx9_pci_mem_high __initdata = 1;
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#else
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int txx9_pci_mem_high __initdata;
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#endif
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/*
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* allocate pci_controller and resources.
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* mem_base, io_base: physical address. 0 for auto assignment.
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* mem_size and io_size means max size on auto assignment.
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* pcic must be &txx9_primary_pcic or NULL.
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*/
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struct pci_controller *__init
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txx9_alloc_pci_controller(struct pci_controller *pcic,
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unsigned long mem_base, unsigned long mem_size,
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unsigned long io_base, unsigned long io_size)
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{
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struct pcic {
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struct pci_controller c;
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struct resource r_mem[2];
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struct resource r_io;
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} *new = NULL;
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int min_size = 0x10000;
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if (!pcic) {
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new = kzalloc(sizeof(*new), GFP_KERNEL);
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if (!new)
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return NULL;
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new->r_mem[0].name = "PCI mem";
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new->r_mem[1].name = "PCI mmio";
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new->r_io.name = "PCI io";
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new->c.mem_resource = new->r_mem;
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new->c.io_resource = &new->r_io;
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pcic = &new->c;
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} else
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BUG_ON(pcic != &txx9_primary_pcic);
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pcic->io_resource->flags = IORESOURCE_IO;
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/*
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* for auto assignment, first search a (big) region for PCI
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* MEM, then search a region for PCI IO.
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*/
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if (mem_base) {
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pcic->mem_resource[0].start = mem_base;
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pcic->mem_resource[0].end = mem_base + mem_size - 1;
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if (request_resource(&iomem_resource, &pcic->mem_resource[0]))
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goto free_and_exit;
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} else {
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unsigned long min = 0, max = 0x20000000; /* low 512MB */
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if (!mem_size) {
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/* default size for auto assignment */
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if (txx9_pci_mem_high)
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mem_size = 0x20000000; /* mem:512M(max) */
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else
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mem_size = 0x08000000; /* mem:128M(max) */
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}
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if (txx9_pci_mem_high) {
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min = 0x20000000;
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max = 0xe0000000;
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}
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/* search free region for PCI MEM */
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for (; mem_size >= min_size; mem_size /= 2) {
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if (allocate_resource(&iomem_resource,
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&pcic->mem_resource[0],
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mem_size, min, max,
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mem_size, NULL, NULL) == 0)
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break;
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}
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if (mem_size < min_size)
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goto free_and_exit;
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}
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pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
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if (io_base) {
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pcic->mem_resource[1].start = io_base;
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pcic->mem_resource[1].end = io_base + io_size - 1;
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if (request_resource(&iomem_resource, &pcic->mem_resource[1]))
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goto release_and_exit;
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} else {
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if (!io_size)
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/* default size for auto assignment */
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io_size = 0x01000000; /* io:16M(max) */
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/* search free region for PCI IO in low 512MB */
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for (; io_size >= min_size; io_size /= 2) {
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if (allocate_resource(&iomem_resource,
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&pcic->mem_resource[1],
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io_size, 0, 0x20000000,
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io_size, NULL, NULL) == 0)
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break;
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}
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if (io_size < min_size)
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goto release_and_exit;
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io_base = pcic->mem_resource[1].start;
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}
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pcic->mem_resource[0].flags = IORESOURCE_MEM;
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if (pcic == &txx9_primary_pcic &&
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mips_io_port_base == (unsigned long)-1) {
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/* map ioport 0 to PCI I/O space address 0 */
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set_io_port_base(IO_BASE + pcic->mem_resource[1].start);
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pcic->io_resource->start = 0;
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pcic->io_offset = 0; /* busaddr == ioaddr */
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pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start;
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} else {
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/* physaddr to ioaddr */
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pcic->io_resource->start =
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io_base - (mips_io_port_base - IO_BASE);
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pcic->io_offset = io_base - (mips_io_port_base - IO_BASE);
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pcic->io_map_base = mips_io_port_base;
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}
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pcic->io_resource->end = pcic->io_resource->start + io_size - 1;
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pcic->mem_offset = 0; /* busaddr == physaddr */
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pr_info("PCI: IO %pR MEM %pR\n", &pcic->mem_resource[1],
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&pcic->mem_resource[0]);
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/* register_pci_controller() will request MEM resource */
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release_resource(&pcic->mem_resource[0]);
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return pcic;
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release_and_exit:
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release_resource(&pcic->mem_resource[0]);
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free_and_exit:
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kfree(new);
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pr_err("PCI: Failed to allocate resources.\n");
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return NULL;
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}
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static int __init
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txx9_arch_pci_init(void)
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{
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PCIBIOS_MIN_IO = 0x8000; /* reseve legacy I/O space */
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return 0;
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}
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arch_initcall(txx9_arch_pci_init);
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/* IRQ/IDSEL mapping */
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int txx9_pci_option =
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#ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT
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TXX9_PCI_OPT_PICMG |
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#endif
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TXX9_PCI_OPT_CLK_AUTO;
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enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT;
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#ifdef CONFIG_TOSHIBA_FPCIB0
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static irqreturn_t i8259_interrupt(int irq, void *dev_id)
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{
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int isairq;
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isairq = i8259_irq();
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if (unlikely(isairq <= I8259A_IRQ_BASE))
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return IRQ_NONE;
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generic_handle_irq(isairq);
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return IRQ_HANDLED;
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}
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static int txx9_i8259_irq_setup(int irq)
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{
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int err;
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init_i8259_irqs();
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err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
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"cascade(i8259)", (void *)(long)irq);
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if (!err)
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pr_info("PCI-ISA bridge PIC (irq %d)\n", irq);
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return err;
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}
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static void __ref quirk_slc90e66_bridge(struct pci_dev *dev)
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{
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int irq; /* PCI/ISA Bridge interrupt */
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u8 reg_64;
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u32 reg_b0;
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u8 reg_e1;
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irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */
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if (!irq)
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return;
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txx9_i8259_irq_setup(irq);
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pci_read_config_byte(dev, 0x64, ®_64);
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pci_read_config_dword(dev, 0xb0, ®_b0);
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pci_read_config_byte(dev, 0xe1, ®_e1);
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/* serial irq control */
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reg_64 = 0xd0;
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/* serial irq pin */
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reg_b0 |= 0x00010000;
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/* ide irq on isa14 */
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reg_e1 &= 0xf0;
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reg_e1 |= 0x0d;
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pci_write_config_byte(dev, 0x64, reg_64);
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pci_write_config_dword(dev, 0xb0, reg_b0);
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pci_write_config_byte(dev, 0xe1, reg_e1);
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smsc_fdc37m81x_init(0x3f0);
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smsc_fdc37m81x_config_beg();
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smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
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SMSC_FDC37M81X_KBD);
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smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
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smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
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smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
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1);
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smsc_fdc37m81x_config_end();
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}
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static void quirk_slc90e66_ide(struct pci_dev *dev)
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{
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unsigned char dat;
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int regs[2] = {0x41, 0x43};
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int i;
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/* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
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pr_info("PCI: %s: IRQ %02x", pci_name(dev), dat);
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/* enable SMSC SLC90E66 IDE */
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for (i = 0; i < ARRAY_SIZE(regs); i++) {
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pci_read_config_byte(dev, regs[i], &dat);
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pci_write_config_byte(dev, regs[i], dat | 0x80);
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pci_read_config_byte(dev, regs[i], &dat);
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pr_cont(" IDETIM%d %02x", i, dat);
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}
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pci_read_config_byte(dev, 0x5c, &dat);
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/*
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* !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
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*
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* This line of code is intended to provide the user with a work
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* around solution to the anomalies cited in SMSC's anomaly sheet
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* entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
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*
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* !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
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*/
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dat |= 0x01;
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pci_write_config_byte(dev, 0x5c, dat);
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pci_read_config_byte(dev, 0x5c, &dat);
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pr_cont(" REG5C %02x\n", dat);
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}
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#endif /* CONFIG_TOSHIBA_FPCIB0 */
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static void tc35815_fixup(struct pci_dev *dev)
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{
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/* This device may have PM registers but not they are not supported. */
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if (dev->pm_cap) {
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dev_info(&dev->dev, "PM disabled\n");
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dev->pm_cap = 0;
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}
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}
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static void final_fixup(struct pci_dev *dev)
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{
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unsigned char bist;
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/* Do build-in self test */
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if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL &&
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(bist & PCI_BIST_CAPABLE)) {
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unsigned long timeout;
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pci_set_power_state(dev, PCI_D0);
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pr_info("PCI: %s BIST...", pci_name(dev));
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pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
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timeout = jiffies + HZ * 2; /* timeout after 2 sec */
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do {
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pci_read_config_byte(dev, PCI_BIST, &bist);
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if (time_after(jiffies, timeout))
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break;
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} while (bist & PCI_BIST_START);
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if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
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pr_cont("failed. (0x%x)\n", bist);
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else
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pr_cont("OK.\n");
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}
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}
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#ifdef CONFIG_TOSHIBA_FPCIB0
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#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
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quirk_slc90e66_bridge);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
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quirk_slc90e66_ide);
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DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
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quirk_slc90e66_ide);
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#endif
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
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PCI_DEVICE_ID_TOSHIBA_TC35815_NWU, tc35815_fixup);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TOSHIBA_2,
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PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939, tc35815_fixup);
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DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
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DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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static int (*txx9_pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
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int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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return txx9_pci_map_irq(dev, slot, pin);
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}
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char * (*txx9_board_pcibios_setup)(char *str) __initdata;
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char *__init txx9_pcibios_setup(char *str)
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{
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if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
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return NULL;
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if (!strcmp(str, "picmg")) {
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/* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
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(5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
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txx9_pci_option |= TXX9_PCI_OPT_PICMG;
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return NULL;
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} else if (!strcmp(str, "nopicmg")) {
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/* non-PICMG compliant backplane (TOSHIBA
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RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
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txx9_pci_option &= ~TXX9_PCI_OPT_PICMG;
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return NULL;
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} else if (!strncmp(str, "clk=", 4)) {
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char *val = str + 4;
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txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK;
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if (strcmp(val, "33") == 0)
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txx9_pci_option |= TXX9_PCI_OPT_CLK_33;
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else if (strcmp(val, "66") == 0)
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txx9_pci_option |= TXX9_PCI_OPT_CLK_66;
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else /* "auto" */
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txx9_pci_option |= TXX9_PCI_OPT_CLK_AUTO;
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return NULL;
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} else if (!strncmp(str, "err=", 4)) {
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if (!strcmp(str + 4, "panic"))
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txx9_pci_err_action = TXX9_PCI_ERR_PANIC;
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else if (!strcmp(str + 4, "ignore"))
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txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
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return NULL;
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}
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txx9_pci_map_irq = txx9_board_vec->pci_map_irq;
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return str;
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}
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