148 lines
5.1 KiB
C
Executable file
148 lines
5.1 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_HASH_H
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#define _ASM_HASH_H
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/*
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* HP-PA only implements integer multiply in the FPU. However, for
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* integer multiplies by constant, it has a number of shift-and-add
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* (but no shift-and-subtract, sigh!) instructions that a compiler
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* can synthesize a code sequence with.
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*
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* Unfortunately, GCC isn't very efficient at using them. For example
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* it uses three instructions for "x *= 21" when only two are needed.
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* But we can find a sequence manually.
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*/
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#define HAVE_ARCH__HASH_32 1
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/*
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* This is a multiply by GOLDEN_RATIO_32 = 0x61C88647 optimized for the
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* PA7100 pairing rules. This is an in-order 2-way superscalar processor.
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* Only one instruction in a pair may be a shift (by more than 3 bits),
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* but other than that, simple ALU ops (including shift-and-add by up
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* to 3 bits) may be paired arbitrarily.
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*
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* PA8xxx processors also dual-issue ALU instructions, although with
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* fewer constraints, so this schedule is good for them, too.
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*
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* This 6-step sequence was found by Yevgen Voronenko's implementation
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* of the Hcub algorithm at http://spiral.ece.cmu.edu/mcm/gen.html.
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*/
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static inline u32 __attribute_const__ __hash_32(u32 x)
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{
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u32 a, b, c;
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/*
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* Phase 1: Compute a = (x << 19) + x,
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* b = (x << 9) + a, c = (x << 23) + b.
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*/
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a = x << 19; /* Two shifts can't be paired */
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b = x << 9; a += x;
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c = x << 23; b += a;
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c += b;
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/* Phase 2: Return (b<<11) + (c<<6) + (a<<3) - c */
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b <<= 11;
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a += c << 3; b -= c;
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return (a << 3) + b;
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}
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#if BITS_PER_LONG == 64
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#define HAVE_ARCH_HASH_64 1
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/*
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* Finding a good shift-and-add chain for GOLDEN_RATIO_64 is tricky,
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* because available software for the purpose chokes on constants this
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* large. (It's mostly designed for compiling FIR filter coefficients
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* into FPGAs.)
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*
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* However, Jason Thong pointed out a work-around. The Hcub software
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* (http://spiral.ece.cmu.edu/mcm/gen.html) is designed for *multiple*
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* constant multiplication, and is good at finding shift-and-add chains
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* which share common terms.
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*
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* Looking at 0x0x61C8864680B583EB in binary:
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* 0110000111001000100001100100011010000000101101011000001111101011
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* \______________/ \__________/ \_______/ \________/
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* \____________________________/ \____________________/
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* you can see the non-zero bits are divided into several well-separated
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* blocks. Hcub can find algorithms for those terms separately, which
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* can then be shifted and added together.
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*
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* Dividing the input into 2, 3 or 4 blocks, Hcub can find solutions
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* with 10, 9 or 8 adds, respectively, making a total of 11 for the
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* whole number.
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*
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* Using just two large blocks, 0xC3910C8D << 31 in the high bits,
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* and 0xB583EB in the low bits, produces as good an algorithm as any,
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* and with one more small shift than alternatives.
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*
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* The high bits are a larger number and more work to compute, as well
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* as needing one extra cycle to shift left 31 bits before the final
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* addition, so they are the critical path for scheduling. The low bits
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* can fit into the scheduling slots left over.
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*/
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/*
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* This _ASSIGN(dst, src) macro performs "dst = src", but prevents GCC
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* from inferring anything about the value assigned to "dest".
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*
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* This prevents it from mis-optimizing certain sequences.
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* In particular, gcc is annoyingly eager to combine consecutive shifts.
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* Given "x <<= 19; y += x; z += x << 1;", GCC will turn this into
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* "y += x << 19; z += x << 20;" even though the latter sequence needs
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* an additional instruction and temporary register.
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*
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* Because no actual assembly code is generated, this construct is
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* usefully portable across all GCC platforms, and so can be test-compiled
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* on non-PA systems.
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*
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* In two places, additional unused input dependencies are added. This
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* forces GCC's scheduling so it does not rearrange instructions too much.
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* Because the PA-8xxx is out of order, I'm not sure how much this matters,
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* but why make it more difficult for the processor than necessary?
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*/
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#define _ASSIGN(dst, src, ...) asm("" : "=r" (dst) : "0" (src), ##__VA_ARGS__)
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/*
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* Multiply by GOLDEN_RATIO_64 = 0x0x61C8864680B583EB using a heavily
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* optimized shift-and-add sequence.
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*
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* Without the final shift, the multiply proper is 19 instructions,
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* 10 cycles and uses only 4 temporaries. Whew!
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*
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* You are not expected to understand this.
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*/
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static __always_inline u32 __attribute_const__
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hash_64(u64 a, unsigned int bits)
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{
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u64 b, c, d;
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/*
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* Encourage GCC to move a dynamic shift to %sar early,
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* thereby freeing up an additional temporary register.
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*/
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if (!__builtin_constant_p(bits))
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asm("" : "=q" (bits) : "0" (64 - bits));
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else
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bits = 64 - bits;
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_ASSIGN(b, a*5); c = a << 13;
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b = (b << 2) + a; _ASSIGN(d, a << 17);
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a = b + (a << 1); c += d;
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d = a << 10; _ASSIGN(a, a << 19);
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d = a - d; _ASSIGN(a, a << 4, "X" (d));
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c += b; a += b;
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d -= c; c += a << 1;
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a += c << 3; _ASSIGN(b, b << (7+31), "X" (c), "X" (d));
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a <<= 31; b += d;
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a += b;
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return a >> bits;
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}
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#undef _ASSIGN /* We're a widely-used header file, so don't litter! */
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#endif /* BITS_PER_LONG == 64 */
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#endif /* _ASM_HASH_H */
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