298 lines
6.8 KiB
Plaintext
Executable file
298 lines
6.8 KiB
Plaintext
Executable file
/*
|
|
* STx/Freescale ADS5125 MPC5125 silicon
|
|
*
|
|
* Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
|
|
*
|
|
* Reworked by Matteo Facchinetti (engineering@sirius-es.it)
|
|
* Copyright (C) 2013 Sirius Electronic Systems
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
|
* option) any later version.
|
|
*/
|
|
|
|
#include <dt-bindings/clock/mpc512x-clock.h>
|
|
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
model = "mpc5125twr"; // In BSP "mpc5125ads"
|
|
compatible = "fsl,mpc5125ads", "fsl,mpc5125";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupt-parent = <&ipic>;
|
|
|
|
aliases {
|
|
gpio0 = &gpio0;
|
|
gpio1 = &gpio1;
|
|
ethernet0 = ð0;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
PowerPC,5125@0 {
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
d-cache-line-size = <0x20>; // 32 bytes
|
|
i-cache-line-size = <0x20>; // 32 bytes
|
|
d-cache-size = <0x8000>; // L1, 32K
|
|
i-cache-size = <0x8000>; // L1, 32K
|
|
timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
|
|
bus-frequency = <198000000>; // 198 MHz csb bus
|
|
clock-frequency = <396000000>; // 396 MHz ppc core
|
|
};
|
|
};
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x00000000 0x10000000>; // 256MB at 0
|
|
};
|
|
|
|
sram@30000000 {
|
|
compatible = "fsl,mpc5121-sram";
|
|
reg = <0x30000000 0x08000>; // 32K at 0x30000000
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
osc: osc {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <33000000>;
|
|
};
|
|
};
|
|
|
|
soc@80000000 {
|
|
compatible = "fsl,mpc5121-immr";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x80000000 0x400000>;
|
|
reg = <0x80000000 0x400000>;
|
|
bus-frequency = <66000000>; // 66 MHz ips bus
|
|
|
|
// IPIC
|
|
// interrupts cell = <intr #, sense>
|
|
// sense values match linux IORESOURCE_IRQ_* defines:
|
|
// sense == 8: Level, low assertion
|
|
// sense == 2: Edge, high-to-low change
|
|
//
|
|
ipic: interrupt-controller@c00 {
|
|
compatible = "fsl,mpc5121-ipic", "fsl,ipic";
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <2>;
|
|
reg = <0xc00 0x100>;
|
|
};
|
|
|
|
rtc@a00 { // Real time clock
|
|
compatible = "fsl,mpc5121-rtc";
|
|
reg = <0xa00 0x100>;
|
|
interrupts = <79 0x8 80 0x8>;
|
|
};
|
|
|
|
reset@e00 { // Reset module
|
|
compatible = "fsl,mpc5125-reset";
|
|
reg = <0xe00 0x100>;
|
|
};
|
|
|
|
clks: clock@f00 { // Clock control
|
|
compatible = "fsl,mpc5121-clock";
|
|
reg = <0xf00 0x100>;
|
|
#clock-cells = <1>;
|
|
clocks = <&osc>;
|
|
clock-names = "osc";
|
|
};
|
|
|
|
pmc@1000{ // Power Management Controller
|
|
compatible = "fsl,mpc5121-pmc";
|
|
reg = <0x1000 0x100>;
|
|
interrupts = <83 0x2>;
|
|
};
|
|
|
|
gpio0: gpio@1100 {
|
|
compatible = "fsl,mpc5125-gpio";
|
|
reg = <0x1100 0x080>;
|
|
interrupts = <78 0x8>;
|
|
};
|
|
|
|
gpio1: gpio@1180 {
|
|
compatible = "fsl,mpc5125-gpio";
|
|
reg = <0x1180 0x080>;
|
|
interrupts = <86 0x8>;
|
|
};
|
|
|
|
can@1300 { // CAN rev.2
|
|
compatible = "fsl,mpc5121-mscan";
|
|
interrupts = <12 0x8>;
|
|
reg = <0x1300 0x80>;
|
|
clocks = <&clks MPC512x_CLK_BDLC>,
|
|
<&clks MPC512x_CLK_IPS>,
|
|
<&clks MPC512x_CLK_SYS>,
|
|
<&clks MPC512x_CLK_REF>,
|
|
<&clks MPC512x_CLK_MSCAN0_MCLK>;
|
|
clock-names = "ipg", "ips", "sys", "ref", "mclk";
|
|
};
|
|
|
|
can@1380 {
|
|
compatible = "fsl,mpc5121-mscan";
|
|
interrupts = <13 0x8>;
|
|
reg = <0x1380 0x80>;
|
|
clocks = <&clks MPC512x_CLK_BDLC>,
|
|
<&clks MPC512x_CLK_IPS>,
|
|
<&clks MPC512x_CLK_SYS>,
|
|
<&clks MPC512x_CLK_REF>,
|
|
<&clks MPC512x_CLK_MSCAN1_MCLK>;
|
|
clock-names = "ipg", "ips", "sys", "ref", "mclk";
|
|
};
|
|
|
|
sdhc@1500 {
|
|
compatible = "fsl,mpc5121-sdhc";
|
|
interrupts = <8 0x8>;
|
|
reg = <0x1500 0x100>;
|
|
clocks = <&clks MPC512x_CLK_IPS>,
|
|
<&clks MPC512x_CLK_SDHC>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
i2c@1700 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
|
|
reg = <0x1700 0x20>;
|
|
interrupts = <0x9 0x8>;
|
|
clocks = <&clks MPC512x_CLK_I2C>;
|
|
clock-names = "ipg";
|
|
};
|
|
|
|
i2c@1720 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
|
|
reg = <0x1720 0x20>;
|
|
interrupts = <0xa 0x8>;
|
|
clocks = <&clks MPC512x_CLK_I2C>;
|
|
clock-names = "ipg";
|
|
};
|
|
|
|
i2c@1740 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,mpc5121-i2c", "fsl-i2c";
|
|
reg = <0x1740 0x20>;
|
|
interrupts = <0xb 0x8>;
|
|
clocks = <&clks MPC512x_CLK_I2C>;
|
|
clock-names = "ipg";
|
|
};
|
|
|
|
i2ccontrol@1760 {
|
|
compatible = "fsl,mpc5121-i2c-ctrl";
|
|
reg = <0x1760 0x8>;
|
|
};
|
|
|
|
diu@2100 {
|
|
compatible = "fsl,mpc5121-diu";
|
|
reg = <0x2100 0x100>;
|
|
interrupts = <64 0x8>;
|
|
clocks = <&clks MPC512x_CLK_DIU>;
|
|
clock-names = "ipg";
|
|
};
|
|
|
|
mdio@2800 {
|
|
compatible = "fsl,mpc5121-fec-mdio";
|
|
reg = <0x2800 0x800>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
phy0: ethernet-phy@0 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
eth0: ethernet@2800 {
|
|
compatible = "fsl,mpc5125-fec";
|
|
reg = <0x2800 0x800>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
interrupts = <4 0x8>;
|
|
phy-handle = < &phy0 >;
|
|
phy-connection-type = "rmii";
|
|
clocks = <&clks MPC512x_CLK_FEC>;
|
|
clock-names = "per";
|
|
};
|
|
|
|
// IO control
|
|
ioctl@a000 {
|
|
compatible = "fsl,mpc5125-ioctl";
|
|
reg = <0xA000 0x1000>;
|
|
};
|
|
|
|
// disable USB1 port
|
|
// TODO:
|
|
// correct pinmux config and fix USB3320 ulpi dependency
|
|
// before re-enabling it
|
|
usb@3000 {
|
|
compatible = "fsl,mpc5121-usb2-dr";
|
|
reg = <0x3000 0x400>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <43 0x8>;
|
|
dr_mode = "host";
|
|
phy_type = "ulpi";
|
|
clocks = <&clks MPC512x_CLK_USB1>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
sclpc@10100 {
|
|
compatible = "fsl,mpc512x-lpbfifo";
|
|
reg = <0x10100 0x50>;
|
|
interrupts = <7 0x8>;
|
|
dmas = <&dma0 26>;
|
|
dma-names = "rx-tx";
|
|
};
|
|
|
|
// 5125 PSCs are not 52xx or 5121 PSC compatible
|
|
// PSC1 uart0 aka ttyPSC0
|
|
serial@11100 {
|
|
compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
|
|
reg = <0x11100 0x100>;
|
|
interrupts = <40 0x8>;
|
|
fsl,rx-fifo-size = <16>;
|
|
fsl,tx-fifo-size = <16>;
|
|
clocks = <&clks MPC512x_CLK_PSC1>,
|
|
<&clks MPC512x_CLK_PSC1_MCLK>;
|
|
clock-names = "ipg", "mclk";
|
|
};
|
|
|
|
// PSC9 uart1 aka ttyPSC1
|
|
serial@11900 {
|
|
compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
|
|
reg = <0x11900 0x100>;
|
|
interrupts = <40 0x8>;
|
|
fsl,rx-fifo-size = <16>;
|
|
fsl,tx-fifo-size = <16>;
|
|
clocks = <&clks MPC512x_CLK_PSC9>,
|
|
<&clks MPC512x_CLK_PSC9_MCLK>;
|
|
clock-names = "ipg", "mclk";
|
|
};
|
|
|
|
pscfifo@11f00 {
|
|
compatible = "fsl,mpc5121-psc-fifo";
|
|
reg = <0x11f00 0x100>;
|
|
interrupts = <40 0x8>;
|
|
clocks = <&clks MPC512x_CLK_PSC_FIFO>;
|
|
clock-names = "ipg";
|
|
};
|
|
|
|
dma0: dma@14000 {
|
|
compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2"
|
|
reg = <0x14000 0x1800>;
|
|
interrupts = <65 0x8>;
|
|
#dma-cells = <1>;
|
|
};
|
|
};
|
|
};
|