407 lines
12 KiB
Plaintext
Executable file
407 lines
12 KiB
Plaintext
Executable file
/*
|
|
* This file supports the Xilinx ML507 board with the 440 processor.
|
|
* A reference design for the FPGA is provided at http://git.xilinx.com.
|
|
*
|
|
* (C) Copyright 2008 Xilinx, Inc.
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public License
|
|
* version 2. This program is licensed "as is" without any warranty of any
|
|
* kind, whether express or implied.
|
|
*
|
|
* ---
|
|
*
|
|
* Device Tree Generator version: 1.1
|
|
*
|
|
* CAUTION: This file is automatically generated by libgen.
|
|
* Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
|
|
*
|
|
* XPS project directory: ml507_ppc440_emb_ref
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "xlnx,virtex440";
|
|
dcr-parent = <&ppc440_0>;
|
|
model = "testing";
|
|
DDR2_SDRAM: memory@0 {
|
|
device_type = "memory";
|
|
reg = < 0 0x10000000 >;
|
|
} ;
|
|
chosen {
|
|
bootargs = "console=ttyS0 root=/dev/ram";
|
|
stdout-path = &RS232_Uart_1;
|
|
} ;
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#cpus = <1>;
|
|
#size-cells = <0>;
|
|
ppc440_0: cpu@0 {
|
|
clock-frequency = <400000000>;
|
|
compatible = "PowerPC,440", "ibm,ppc440";
|
|
d-cache-line-size = <0x20>;
|
|
d-cache-size = <0x8000>;
|
|
dcr-access-method = "native";
|
|
dcr-controller ;
|
|
device_type = "cpu";
|
|
i-cache-line-size = <0x20>;
|
|
i-cache-size = <0x8000>;
|
|
model = "PowerPC,440";
|
|
reg = <0>;
|
|
timebase-frequency = <400000000>;
|
|
xlnx,apu-control = <1>;
|
|
xlnx,apu-udi-0 = <0>;
|
|
xlnx,apu-udi-1 = <0>;
|
|
xlnx,apu-udi-10 = <0>;
|
|
xlnx,apu-udi-11 = <0>;
|
|
xlnx,apu-udi-12 = <0>;
|
|
xlnx,apu-udi-13 = <0>;
|
|
xlnx,apu-udi-14 = <0>;
|
|
xlnx,apu-udi-15 = <0>;
|
|
xlnx,apu-udi-2 = <0>;
|
|
xlnx,apu-udi-3 = <0>;
|
|
xlnx,apu-udi-4 = <0>;
|
|
xlnx,apu-udi-5 = <0>;
|
|
xlnx,apu-udi-6 = <0>;
|
|
xlnx,apu-udi-7 = <0>;
|
|
xlnx,apu-udi-8 = <0>;
|
|
xlnx,apu-udi-9 = <0>;
|
|
xlnx,dcr-autolock-enable = <1>;
|
|
xlnx,dcu-rd-ld-cache-plb-prio = <0>;
|
|
xlnx,dcu-rd-noncache-plb-prio = <0>;
|
|
xlnx,dcu-rd-touch-plb-prio = <0>;
|
|
xlnx,dcu-rd-urgent-plb-prio = <0>;
|
|
xlnx,dcu-wr-flush-plb-prio = <0>;
|
|
xlnx,dcu-wr-store-plb-prio = <0>;
|
|
xlnx,dcu-wr-urgent-plb-prio = <0>;
|
|
xlnx,dma0-control = <0>;
|
|
xlnx,dma0-plb-prio = <0>;
|
|
xlnx,dma0-rxchannelctrl = <0x1010000>;
|
|
xlnx,dma0-rxirqtimer = <0x3ff>;
|
|
xlnx,dma0-txchannelctrl = <0x1010000>;
|
|
xlnx,dma0-txirqtimer = <0x3ff>;
|
|
xlnx,dma1-control = <0>;
|
|
xlnx,dma1-plb-prio = <0>;
|
|
xlnx,dma1-rxchannelctrl = <0x1010000>;
|
|
xlnx,dma1-rxirqtimer = <0x3ff>;
|
|
xlnx,dma1-txchannelctrl = <0x1010000>;
|
|
xlnx,dma1-txirqtimer = <0x3ff>;
|
|
xlnx,dma2-control = <0>;
|
|
xlnx,dma2-plb-prio = <0>;
|
|
xlnx,dma2-rxchannelctrl = <0x1010000>;
|
|
xlnx,dma2-rxirqtimer = <0x3ff>;
|
|
xlnx,dma2-txchannelctrl = <0x1010000>;
|
|
xlnx,dma2-txirqtimer = <0x3ff>;
|
|
xlnx,dma3-control = <0>;
|
|
xlnx,dma3-plb-prio = <0>;
|
|
xlnx,dma3-rxchannelctrl = <0x1010000>;
|
|
xlnx,dma3-rxirqtimer = <0x3ff>;
|
|
xlnx,dma3-txchannelctrl = <0x1010000>;
|
|
xlnx,dma3-txirqtimer = <0x3ff>;
|
|
xlnx,endian-reset = <0>;
|
|
xlnx,generate-plb-timespecs = <1>;
|
|
xlnx,icu-rd-fetch-plb-prio = <0>;
|
|
xlnx,icu-rd-spec-plb-prio = <0>;
|
|
xlnx,icu-rd-touch-plb-prio = <0>;
|
|
xlnx,interconnect-imask = <0xffffffff>;
|
|
xlnx,mplb-allow-lock-xfer = <1>;
|
|
xlnx,mplb-arb-mode = <0>;
|
|
xlnx,mplb-awidth = <0x20>;
|
|
xlnx,mplb-counter = <0x500>;
|
|
xlnx,mplb-dwidth = <0x80>;
|
|
xlnx,mplb-max-burst = <8>;
|
|
xlnx,mplb-native-dwidth = <0x80>;
|
|
xlnx,mplb-p2p = <0>;
|
|
xlnx,mplb-prio-dcur = <2>;
|
|
xlnx,mplb-prio-dcuw = <3>;
|
|
xlnx,mplb-prio-icu = <4>;
|
|
xlnx,mplb-prio-splb0 = <1>;
|
|
xlnx,mplb-prio-splb1 = <0>;
|
|
xlnx,mplb-read-pipe-enable = <1>;
|
|
xlnx,mplb-sync-tattribute = <0>;
|
|
xlnx,mplb-wdog-enable = <1>;
|
|
xlnx,mplb-write-pipe-enable = <1>;
|
|
xlnx,mplb-write-post-enable = <1>;
|
|
xlnx,num-dma = <1>;
|
|
xlnx,pir = <0xf>;
|
|
xlnx,ppc440mc-addr-base = <0>;
|
|
xlnx,ppc440mc-addr-high = <0xfffffff>;
|
|
xlnx,ppc440mc-arb-mode = <0>;
|
|
xlnx,ppc440mc-bank-conflict-mask = <0xc00000>;
|
|
xlnx,ppc440mc-control = <0xf810008f>;
|
|
xlnx,ppc440mc-max-burst = <8>;
|
|
xlnx,ppc440mc-prio-dcur = <2>;
|
|
xlnx,ppc440mc-prio-dcuw = <3>;
|
|
xlnx,ppc440mc-prio-icu = <4>;
|
|
xlnx,ppc440mc-prio-splb0 = <1>;
|
|
xlnx,ppc440mc-prio-splb1 = <0>;
|
|
xlnx,ppc440mc-row-conflict-mask = <0x3ffe00>;
|
|
xlnx,ppcdm-asyncmode = <0>;
|
|
xlnx,ppcds-asyncmode = <0>;
|
|
xlnx,user-reset = <0>;
|
|
DMA0: sdma@80 {
|
|
compatible = "xlnx,ll-dma-1.00.a";
|
|
dcr-reg = < 0x80 0x11 >;
|
|
interrupt-parent = <&xps_intc_0>;
|
|
interrupts = < 10 2 11 2 >;
|
|
} ;
|
|
} ;
|
|
} ;
|
|
plb_v46_0: plb@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
|
|
ranges ;
|
|
DIP_Switches_8Bit: gpio@81460000 {
|
|
compatible = "xlnx,xps-gpio-1.00.a";
|
|
interrupt-parent = <&xps_intc_0>;
|
|
interrupts = < 7 2 >;
|
|
reg = < 0x81460000 0x10000 >;
|
|
xlnx,all-inputs = <1>;
|
|
xlnx,all-inputs-2 = <0>;
|
|
xlnx,dout-default = <0>;
|
|
xlnx,dout-default-2 = <0>;
|
|
xlnx,family = "virtex5";
|
|
xlnx,gpio-width = <8>;
|
|
xlnx,interrupt-present = <1>;
|
|
xlnx,is-bidir = <1>;
|
|
xlnx,is-bidir-2 = <1>;
|
|
xlnx,is-dual = <0>;
|
|
xlnx,tri-default = <0xffffffff>;
|
|
xlnx,tri-default-2 = <0xffffffff>;
|
|
} ;
|
|
FLASH: flash@fc000000 {
|
|
bank-width = <2>;
|
|
compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
|
|
reg = < 0xfc000000 0x2000000 >;
|
|
xlnx,family = "virtex5";
|
|
xlnx,include-datawidth-matching-0 = <0x1>;
|
|
xlnx,include-datawidth-matching-1 = <0x0>;
|
|
xlnx,include-datawidth-matching-2 = <0x0>;
|
|
xlnx,include-datawidth-matching-3 = <0x0>;
|
|
xlnx,include-negedge-ioregs = <0x0>;
|
|
xlnx,include-plb-ipif = <0x1>;
|
|
xlnx,include-wrbuf = <0x1>;
|
|
xlnx,max-mem-width = <0x10>;
|
|
xlnx,mch-native-dwidth = <0x20>;
|
|
xlnx,mch-plb-clk-period-ps = <0x2710>;
|
|
xlnx,mch-splb-awidth = <0x20>;
|
|
xlnx,mch0-accessbuf-depth = <0x10>;
|
|
xlnx,mch0-protocol = <0x0>;
|
|
xlnx,mch0-rddatabuf-depth = <0x10>;
|
|
xlnx,mch1-accessbuf-depth = <0x10>;
|
|
xlnx,mch1-protocol = <0x0>;
|
|
xlnx,mch1-rddatabuf-depth = <0x10>;
|
|
xlnx,mch2-accessbuf-depth = <0x10>;
|
|
xlnx,mch2-protocol = <0x0>;
|
|
xlnx,mch2-rddatabuf-depth = <0x10>;
|
|
xlnx,mch3-accessbuf-depth = <0x10>;
|
|
xlnx,mch3-protocol = <0x0>;
|
|
xlnx,mch3-rddatabuf-depth = <0x10>;
|
|
xlnx,mem0-width = <0x10>;
|
|
xlnx,mem1-width = <0x20>;
|
|
xlnx,mem2-width = <0x20>;
|
|
xlnx,mem3-width = <0x20>;
|
|
xlnx,num-banks-mem = <0x1>;
|
|
xlnx,num-channels = <0x2>;
|
|
xlnx,priority-mode = <0x0>;
|
|
xlnx,synch-mem-0 = <0x0>;
|
|
xlnx,synch-mem-1 = <0x0>;
|
|
xlnx,synch-mem-2 = <0x0>;
|
|
xlnx,synch-mem-3 = <0x0>;
|
|
xlnx,synch-pipedelay-0 = <0x2>;
|
|
xlnx,synch-pipedelay-1 = <0x2>;
|
|
xlnx,synch-pipedelay-2 = <0x2>;
|
|
xlnx,synch-pipedelay-3 = <0x2>;
|
|
xlnx,tavdv-ps-mem-0 = <0x1adb0>;
|
|
xlnx,tavdv-ps-mem-1 = <0x3a98>;
|
|
xlnx,tavdv-ps-mem-2 = <0x3a98>;
|
|
xlnx,tavdv-ps-mem-3 = <0x3a98>;
|
|
xlnx,tcedv-ps-mem-0 = <0x1adb0>;
|
|
xlnx,tcedv-ps-mem-1 = <0x3a98>;
|
|
xlnx,tcedv-ps-mem-2 = <0x3a98>;
|
|
xlnx,tcedv-ps-mem-3 = <0x3a98>;
|
|
xlnx,thzce-ps-mem-0 = <0x88b8>;
|
|
xlnx,thzce-ps-mem-1 = <0x1b58>;
|
|
xlnx,thzce-ps-mem-2 = <0x1b58>;
|
|
xlnx,thzce-ps-mem-3 = <0x1b58>;
|
|
xlnx,thzoe-ps-mem-0 = <0x1b58>;
|
|
xlnx,thzoe-ps-mem-1 = <0x1b58>;
|
|
xlnx,thzoe-ps-mem-2 = <0x1b58>;
|
|
xlnx,thzoe-ps-mem-3 = <0x1b58>;
|
|
xlnx,tlzwe-ps-mem-0 = <0x88b8>;
|
|
xlnx,tlzwe-ps-mem-1 = <0x0>;
|
|
xlnx,tlzwe-ps-mem-2 = <0x0>;
|
|
xlnx,tlzwe-ps-mem-3 = <0x0>;
|
|
xlnx,twc-ps-mem-0 = <0x2af8>;
|
|
xlnx,twc-ps-mem-1 = <0x3a98>;
|
|
xlnx,twc-ps-mem-2 = <0x3a98>;
|
|
xlnx,twc-ps-mem-3 = <0x3a98>;
|
|
xlnx,twp-ps-mem-0 = <0x11170>;
|
|
xlnx,twp-ps-mem-1 = <0x2ee0>;
|
|
xlnx,twp-ps-mem-2 = <0x2ee0>;
|
|
xlnx,twp-ps-mem-3 = <0x2ee0>;
|
|
xlnx,xcl0-linesize = <0x4>;
|
|
xlnx,xcl0-writexfer = <0x1>;
|
|
xlnx,xcl1-linesize = <0x4>;
|
|
xlnx,xcl1-writexfer = <0x1>;
|
|
xlnx,xcl2-linesize = <0x4>;
|
|
xlnx,xcl2-writexfer = <0x1>;
|
|
xlnx,xcl3-linesize = <0x4>;
|
|
xlnx,xcl3-writexfer = <0x1>;
|
|
} ;
|
|
Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "xlnx,compound";
|
|
ethernet@81c00000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "xlnx,xps-ll-temac-1.01.b";
|
|
device_type = "network";
|
|
interrupt-parent = <&xps_intc_0>;
|
|
interrupts = < 5 2 >;
|
|
llink-connected = <&DMA0>;
|
|
local-mac-address = [ 02 00 00 00 00 00 ];
|
|
reg = < 0x81c00000 0x40 >;
|
|
xlnx,bus2core-clk-ratio = <1>;
|
|
xlnx,phy-type = <1>;
|
|
xlnx,phyaddr = <1>;
|
|
xlnx,rxcsum = <1>;
|
|
xlnx,rxfifo = <0x1000>;
|
|
xlnx,temac-type = <0>;
|
|
xlnx,txcsum = <1>;
|
|
xlnx,txfifo = <0x1000>;
|
|
phy-handle = <&phy7>;
|
|
clock-frequency = <100000000>;
|
|
phy7: phy@7 {
|
|
compatible = "marvell,88e1111";
|
|
reg = <7>;
|
|
} ;
|
|
} ;
|
|
} ;
|
|
IIC_EEPROM: i2c@81600000 {
|
|
compatible = "xlnx,xps-iic-2.00.a";
|
|
interrupt-parent = <&xps_intc_0>;
|
|
interrupts = < 6 2 >;
|
|
reg = < 0x81600000 0x10000 >;
|
|
xlnx,clk-freq = <0x5f5e100>;
|
|
xlnx,family = "virtex5";
|
|
xlnx,gpo-width = <0x1>;
|
|
xlnx,iic-freq = <0x186a0>;
|
|
xlnx,scl-inertial-delay = <0x0>;
|
|
xlnx,sda-inertial-delay = <0x0>;
|
|
xlnx,ten-bit-adr = <0x0>;
|
|
} ;
|
|
LEDs_8Bit: gpio@81400000 {
|
|
compatible = "xlnx,xps-gpio-1.00.a";
|
|
reg = < 0x81400000 0x10000 >;
|
|
xlnx,all-inputs = <0>;
|
|
xlnx,all-inputs-2 = <0>;
|
|
xlnx,dout-default = <0>;
|
|
xlnx,dout-default-2 = <0>;
|
|
xlnx,family = "virtex5";
|
|
xlnx,gpio-width = <8>;
|
|
xlnx,interrupt-present = <0>;
|
|
xlnx,is-bidir = <1>;
|
|
xlnx,is-bidir-2 = <1>;
|
|
xlnx,is-dual = <0>;
|
|
xlnx,tri-default = <0xffffffff>;
|
|
xlnx,tri-default-2 = <0xffffffff>;
|
|
} ;
|
|
LEDs_Positions: gpio@81420000 {
|
|
compatible = "xlnx,xps-gpio-1.00.a";
|
|
reg = < 0x81420000 0x10000 >;
|
|
xlnx,all-inputs = <0>;
|
|
xlnx,all-inputs-2 = <0>;
|
|
xlnx,dout-default = <0>;
|
|
xlnx,dout-default-2 = <0>;
|
|
xlnx,family = "virtex5";
|
|
xlnx,gpio-width = <5>;
|
|
xlnx,interrupt-present = <0>;
|
|
xlnx,is-bidir = <1>;
|
|
xlnx,is-bidir-2 = <1>;
|
|
xlnx,is-dual = <0>;
|
|
xlnx,tri-default = <0xffffffff>;
|
|
xlnx,tri-default-2 = <0xffffffff>;
|
|
} ;
|
|
Push_Buttons_5Bit: gpio@81440000 {
|
|
compatible = "xlnx,xps-gpio-1.00.a";
|
|
interrupt-parent = <&xps_intc_0>;
|
|
interrupts = < 8 2 >;
|
|
reg = < 0x81440000 0x10000 >;
|
|
xlnx,all-inputs = <1>;
|
|
xlnx,all-inputs-2 = <0>;
|
|
xlnx,dout-default = <0>;
|
|
xlnx,dout-default-2 = <0>;
|
|
xlnx,family = "virtex5";
|
|
xlnx,gpio-width = <5>;
|
|
xlnx,interrupt-present = <1>;
|
|
xlnx,is-bidir = <1>;
|
|
xlnx,is-bidir-2 = <1>;
|
|
xlnx,is-dual = <0>;
|
|
xlnx,tri-default = <0xffffffff>;
|
|
xlnx,tri-default-2 = <0xffffffff>;
|
|
} ;
|
|
RS232_Uart_1: serial@83e00000 {
|
|
clock-frequency = <100000000>;
|
|
compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
|
|
current-speed = <9600>;
|
|
device_type = "serial";
|
|
interrupt-parent = <&xps_intc_0>;
|
|
interrupts = < 9 2 >;
|
|
reg = < 0x83e00000 0x10000 >;
|
|
reg-offset = <0x1003>;
|
|
reg-shift = <2>;
|
|
xlnx,family = "virtex5";
|
|
xlnx,has-external-rclk = <0>;
|
|
xlnx,has-external-xin = <0>;
|
|
xlnx,is-a-16550 = <1>;
|
|
} ;
|
|
SysACE_CompactFlash: sysace@83600000 {
|
|
compatible = "xlnx,xps-sysace-1.00.a";
|
|
interrupt-parent = <&xps_intc_0>;
|
|
interrupts = < 4 2 >;
|
|
reg = < 0x83600000 0x10000 >;
|
|
xlnx,family = "virtex5";
|
|
xlnx,mem-width = <0x10>;
|
|
} ;
|
|
xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
|
|
compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
|
|
reg = < 0xffff0000 0x10000 >;
|
|
xlnx,family = "virtex5";
|
|
} ;
|
|
xps_intc_0: interrupt-controller@81800000 {
|
|
#interrupt-cells = <2>;
|
|
compatible = "xlnx,xps-intc-1.00.a";
|
|
interrupt-controller ;
|
|
reg = < 0x81800000 0x10000 >;
|
|
xlnx,num-intr-inputs = <0xc>;
|
|
} ;
|
|
xps_timebase_wdt_1: xps-timebase-wdt@83a00000 {
|
|
compatible = "xlnx,xps-timebase-wdt-1.00.b";
|
|
interrupt-parent = <&xps_intc_0>;
|
|
interrupts = < 2 0 1 2 >;
|
|
reg = < 0x83a00000 0x10000 >;
|
|
xlnx,family = "virtex5";
|
|
xlnx,wdt-enable-once = <0>;
|
|
xlnx,wdt-interval = <0x1e>;
|
|
} ;
|
|
xps_timer_1: timer@83c00000 {
|
|
compatible = "xlnx,xps-timer-1.00.a";
|
|
interrupt-parent = <&xps_intc_0>;
|
|
interrupts = < 3 2 >;
|
|
reg = < 0x83c00000 0x10000 >;
|
|
xlnx,count-width = <0x20>;
|
|
xlnx,family = "virtex5";
|
|
xlnx,gen0-assert = <1>;
|
|
xlnx,gen1-assert = <1>;
|
|
xlnx,one-timer-only = <1>;
|
|
xlnx,trig0-assert = <1>;
|
|
xlnx,trig1-assert = <1>;
|
|
} ;
|
|
} ;
|
|
} ;
|