c05564c4d8
Android 13
185 lines
4.1 KiB
C
Executable file
185 lines
4.1 KiB
C
Executable file
/*
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* udbg for zilog scc ports as found on Apple PowerMacs
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*
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* Copyright (C) 2001-2005 PPC 64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <asm/udbg.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pmac_feature.h>
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extern u8 real_readb(volatile u8 __iomem *addr);
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extern void real_writeb(u8 data, volatile u8 __iomem *addr);
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#define SCC_TXRDY 4
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#define SCC_RXRDY 1
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static volatile u8 __iomem *sccc;
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static volatile u8 __iomem *sccd;
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static void udbg_scc_putc(char c)
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{
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if (sccc) {
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while ((in_8(sccc) & SCC_TXRDY) == 0)
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;
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out_8(sccd, c);
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if (c == '\n')
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udbg_scc_putc('\r');
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}
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}
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static int udbg_scc_getc_poll(void)
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{
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if (sccc) {
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if ((in_8(sccc) & SCC_RXRDY) != 0)
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return in_8(sccd);
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else
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return -1;
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}
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return -1;
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}
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static int udbg_scc_getc(void)
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{
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if (sccc) {
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while ((in_8(sccc) & SCC_RXRDY) == 0)
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;
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return in_8(sccd);
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}
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return -1;
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}
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static unsigned char scc_inittab[] = {
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13, 0, /* set baud rate divisor */
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12, 0,
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14, 1, /* baud rate gen enable, src=rtxc */
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11, 0x50, /* clocks = br gen */
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5, 0xea, /* tx 8 bits, assert DTR & RTS */
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4, 0x46, /* x16 clock, 1 stop */
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3, 0xc1, /* rx enable, 8 bits */
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};
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void udbg_scc_init(int force_scc)
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{
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const u32 *reg;
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unsigned long addr;
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struct device_node *stdout = NULL, *escc = NULL, *macio = NULL;
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struct device_node *ch, *ch_def = NULL, *ch_a = NULL;
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const char *path;
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int i;
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escc = of_find_node_by_name(NULL, "escc");
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if (escc == NULL)
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goto bail;
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macio = of_get_parent(escc);
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if (macio == NULL)
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goto bail;
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path = of_get_property(of_chosen, "linux,stdout-path", NULL);
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if (path != NULL)
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stdout = of_find_node_by_path(path);
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for (ch = NULL; (ch = of_get_next_child(escc, ch)) != NULL;) {
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if (ch == stdout)
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ch_def = of_node_get(ch);
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if (strcmp(ch->name, "ch-a") == 0)
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ch_a = of_node_get(ch);
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}
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if (ch_def == NULL && !force_scc)
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goto bail;
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ch = ch_def ? ch_def : ch_a;
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/* Get address within mac-io ASIC */
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reg = of_get_property(escc, "reg", NULL);
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if (reg == NULL)
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goto bail;
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addr = reg[0];
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/* Get address of mac-io PCI itself */
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reg = of_get_property(macio, "assigned-addresses", NULL);
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if (reg == NULL)
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goto bail;
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addr += reg[2];
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/* Lock the serial port */
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pmac_call_feature(PMAC_FTR_SCC_ENABLE, ch,
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PMAC_SCC_ASYNC | PMAC_SCC_FLAG_XMON, 1);
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if (ch == ch_a)
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addr += 0x20;
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sccc = ioremap(addr & PAGE_MASK, PAGE_SIZE) ;
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sccc += addr & ~PAGE_MASK;
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sccd = sccc + 0x10;
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mb();
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for (i = 20000; i != 0; --i)
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in_8(sccc);
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out_8(sccc, 0x09); /* reset A or B side */
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out_8(sccc, 0xc0);
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/* If SCC was the OF output port, read the BRG value, else
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* Setup for 38400 or 57600 8N1 depending on the machine
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*/
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if (ch_def != NULL) {
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out_8(sccc, 13);
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scc_inittab[1] = in_8(sccc);
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out_8(sccc, 12);
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scc_inittab[3] = in_8(sccc);
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} else if (of_machine_is_compatible("RackMac1,1")
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|| of_machine_is_compatible("RackMac1,2")
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|| of_machine_is_compatible("MacRISC4")) {
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/* Xserves and G5s default to 57600 */
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scc_inittab[1] = 0;
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scc_inittab[3] = 0;
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} else {
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/* Others default to 38400 */
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scc_inittab[1] = 0;
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scc_inittab[3] = 1;
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}
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for (i = 0; i < sizeof(scc_inittab); ++i)
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out_8(sccc, scc_inittab[i]);
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udbg_putc = udbg_scc_putc;
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udbg_getc = udbg_scc_getc;
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udbg_getc_poll = udbg_scc_getc_poll;
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udbg_puts("Hello World !\n");
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bail:
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of_node_put(macio);
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of_node_put(escc);
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of_node_put(stdout);
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of_node_put(ch_def);
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of_node_put(ch_a);
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}
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#ifdef CONFIG_PPC64
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static void udbg_real_scc_putc(char c)
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{
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while ((real_readb(sccc) & SCC_TXRDY) == 0)
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;
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real_writeb(c, sccd);
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if (c == '\n')
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udbg_real_scc_putc('\r');
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}
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void __init udbg_init_pmac_realmode(void)
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{
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sccc = (volatile u8 __iomem *)0x80013020ul;
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sccd = (volatile u8 __iomem *)0x80013030ul;
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udbg_putc = udbg_real_scc_putc;
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udbg_getc = NULL;
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udbg_getc_poll = NULL;
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}
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#endif /* CONFIG_PPC64 */
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