114 lines
4.1 KiB
C
Executable file
114 lines
4.1 KiB
C
Executable file
// SPDX-License-Identifier: GPL-2.0
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/sh_intc.h>
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#include "pci-sh4.h"
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int pcibios_map_platform_irq(const struct pci_dev *, u8 slot, u8 pin)
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{
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switch (slot) {
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case 0: return evt2irq(0x3a0);
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case 1: return evt2irq(0x3a0); /* AMD Ethernet controller */
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case 2: return -1;
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case 3: return -1;
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case 4: return -1;
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default:
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printk("PCI: Bad IRQ mapping request for slot %d\n", slot);
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return -1;
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}
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}
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#define PCIMCR_MRSET_OFF 0xBFFFFFFF
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#define PCIMCR_RFSH_OFF 0xFFFFFFFB
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/*
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* Only long word accesses of the PCIC's internal local registers and the
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* configuration registers from the CPU is supported.
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*/
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#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
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#define PCIC_READ(x) readl(PCI_REG(x))
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/*
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* Description: This function sets up and initializes the pcic, sets
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* up the BARS, maps the DRAM into the address space etc, etc.
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*/
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int pci_fixup_pcic(struct pci_channel *chan)
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{
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unsigned long bcr1, wcr1, wcr2, wcr3, mcr;
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unsigned short bcr2;
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/*
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* Initialize the slave bus controller on the pcic. The values used
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* here should not be hardcoded, but they should be taken from the bsc
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* on the processor, to make this function as generic as possible.
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* (i.e. Another sbc may usr different SDRAM timing settings -- in order
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* for the pcic to work, its settings need to be exactly the same.)
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*/
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bcr1 = (*(volatile unsigned long*)(SH7751_BCR1));
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bcr2 = (*(volatile unsigned short*)(SH7751_BCR2));
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wcr1 = (*(volatile unsigned long*)(SH7751_WCR1));
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wcr2 = (*(volatile unsigned long*)(SH7751_WCR2));
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wcr3 = (*(volatile unsigned long*)(SH7751_WCR3));
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mcr = (*(volatile unsigned long*)(SH7751_MCR));
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bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */
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(*(volatile unsigned long*)(SH7751_BCR1)) = bcr1;
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bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
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PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */
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PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */
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PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */
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PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */
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PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */
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mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
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PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
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/* Enable all interrupts, so we know what to fix */
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PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);
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PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);
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/* Set up standard PCI config registers */
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PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */
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PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */
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PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */
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PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */
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PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */
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PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */
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PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */
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PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */
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PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */
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PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */
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/* Now turn it on... */
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PCIC_WRITE(SH7751_PCICR, 0xa5000001);
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/*
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* Set PCIMBR and PCIIOBR here, assuming a single window
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* (16M MEM, 256K IO) is enough. If a larger space is
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* needed, the readx/writex and inx/outx functions will
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* have to do more (e.g. setting registers for each call).
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*/
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/*
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* Set the MBR so PCI address is one-to-one with window,
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* meaning all calls go straight through... use BUG_ON to
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* catch erroneous assumption.
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*/
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BUG_ON(chan->resources[1].start != SH7751_PCI_MEMORY_BASE);
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PCIC_WRITE(SH7751_PCIMBR, chan->resources[1].start);
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/* Set IOBR for window containing area specified in pci.h */
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PCIC_WRITE(SH7751_PCIIOBR, (chan->resources[0].start & SH7751_PCIIOBR_MASK));
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/* All done, may as well say so... */
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printk("SH7751 PCI: Finished initialization of the PCI controller\n");
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return 1;
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}
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