178 lines
5.2 KiB
C
Executable file
178 lines
5.2 KiB
C
Executable file
/*
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* Renesas MX-G (R8A03022BG) Setup
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*
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* Copyright (C) 2008, 2009 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15,
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PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
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SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1,
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SCIF0, SCIF1,
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MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5,
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MTU2_TGI3B, MTU2_TGI3C,
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/* interrupt groups */
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PINT,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
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INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
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INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
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INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
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INTC_IRQ(IRQ8, 72), INTC_IRQ(IRQ9, 73),
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INTC_IRQ(IRQ10, 74), INTC_IRQ(IRQ11, 75),
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INTC_IRQ(IRQ12, 76), INTC_IRQ(IRQ13, 77),
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INTC_IRQ(IRQ14, 78), INTC_IRQ(IRQ15, 79),
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INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
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INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
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INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
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INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
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INTC_IRQ(SINT8, 94), INTC_IRQ(SINT7, 95),
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INTC_IRQ(SINT6, 96), INTC_IRQ(SINT5, 97),
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INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99),
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INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101),
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INTC_IRQ(SCIF0, 220), INTC_IRQ(SCIF0, 221),
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INTC_IRQ(SCIF0, 222), INTC_IRQ(SCIF0, 223),
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INTC_IRQ(SCIF1, 224), INTC_IRQ(SCIF1, 225),
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INTC_IRQ(SCIF1, 226), INTC_IRQ(SCIF1, 227),
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INTC_IRQ(MTU2_GROUP1, 228), INTC_IRQ(MTU2_GROUP1, 229),
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INTC_IRQ(MTU2_GROUP1, 230), INTC_IRQ(MTU2_GROUP1, 231),
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INTC_IRQ(MTU2_GROUP1, 232), INTC_IRQ(MTU2_GROUP1, 233),
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INTC_IRQ(MTU2_GROUP2, 234), INTC_IRQ(MTU2_GROUP2, 235),
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INTC_IRQ(MTU2_GROUP2, 236), INTC_IRQ(MTU2_GROUP2, 237),
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INTC_IRQ(MTU2_GROUP2, 238), INTC_IRQ(MTU2_GROUP2, 239),
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INTC_IRQ(MTU2_GROUP3, 240), INTC_IRQ(MTU2_GROUP3, 241),
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INTC_IRQ(MTU2_GROUP3, 242), INTC_IRQ(MTU2_GROUP3, 243),
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INTC_IRQ(MTU2_TGI3B, 244),
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INTC_IRQ(MTU2_TGI3C, 245),
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INTC_IRQ(MTU2_GROUP4, 246), INTC_IRQ(MTU2_GROUP4, 247),
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INTC_IRQ(MTU2_GROUP4, 248), INTC_IRQ(MTU2_GROUP4, 249),
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INTC_IRQ(MTU2_GROUP4, 250), INTC_IRQ(MTU2_GROUP4, 251),
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INTC_IRQ(MTU2_GROUP5, 252), INTC_IRQ(MTU2_GROUP5, 253),
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INTC_IRQ(MTU2_GROUP5, 254), INTC_IRQ(MTU2_GROUP5, 255),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
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PINT4, PINT5, PINT6, PINT7),
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffd9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
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{ 0xfffd941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
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{ 0xfffd941c, 0, 16, 4, /* IPR03 */ { IRQ8, IRQ9, IRQ10, IRQ11 } },
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{ 0xfffd941e, 0, 16, 4, /* IPR04 */ { IRQ12, IRQ13, IRQ14, IRQ15 } },
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{ 0xfffd9420, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
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{ 0xfffd9800, 0, 16, 4, /* IPR06 */ { } },
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{ 0xfffd9802, 0, 16, 4, /* IPR07 */ { } },
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{ 0xfffd9804, 0, 16, 4, /* IPR08 */ { } },
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{ 0xfffd9806, 0, 16, 4, /* IPR09 */ { } },
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{ 0xfffd9808, 0, 16, 4, /* IPR10 */ { } },
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{ 0xfffd980a, 0, 16, 4, /* IPR11 */ { } },
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{ 0xfffd980c, 0, 16, 4, /* IPR12 */ { } },
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{ 0xfffd980e, 0, 16, 4, /* IPR13 */ { } },
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{ 0xfffd9810, 0, 16, 4, /* IPR14 */ { 0, 0, 0, SCIF0 } },
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{ 0xfffd9812, 0, 16, 4, /* IPR15 */
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{ SCIF1, MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3 } },
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{ 0xfffd9814, 0, 16, 4, /* IPR16 */
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{ MTU2_TGI3B, MTU2_TGI3C, MTU2_GROUP4, MTU2_GROUP5 } },
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xfffd9408, 0, 16, /* PINTER */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
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};
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static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
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mask_registers, prio_registers, NULL);
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static struct resource mtu2_resources[] = {
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DEFINE_RES_MEM(0xff801000, 0x400),
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DEFINE_RES_IRQ_NAMED(228, "tgi0a"),
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DEFINE_RES_IRQ_NAMED(234, "tgi1a"),
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DEFINE_RES_IRQ_NAMED(240, "tgi2a"),
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};
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static struct platform_device mtu2_device = {
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.name = "sh-mtu2",
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.id = -1,
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.resource = mtu2_resources,
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.num_resources = ARRAY_SIZE(mtu2_resources),
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};
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static struct plat_sci_port scif0_platform_data = {
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.scscr = SCSCR_REIE,
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.type = PORT_SCIF,
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};
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static struct resource scif0_resources[] = {
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DEFINE_RES_MEM(0xff804000, 0x100),
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DEFINE_RES_IRQ(220),
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.resource = scif0_resources,
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.num_resources = ARRAY_SIZE(scif0_resources),
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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static struct platform_device *mxg_devices[] __initdata = {
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&scif0_device,
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&mtu2_device,
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};
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static int __init mxg_devices_setup(void)
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{
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return platform_add_devices(mxg_devices,
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ARRAY_SIZE(mxg_devices));
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}
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arch_initcall(mxg_devices_setup);
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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}
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static struct platform_device *mxg_early_devices[] __initdata = {
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&scif0_device,
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&mtu2_device,
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};
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void __init plat_early_device_setup(void)
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{
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early_platform_add_devices(mxg_early_devices,
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ARRAY_SIZE(mxg_early_devices));
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}
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