149 lines
3.6 KiB
C
Executable file
149 lines
3.6 KiB
C
Executable file
/*
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* SH-X3 SMP
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*
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* Copyright (C) 2007 - 2010 Paul Mundt
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* Copyright (C) 2007 Magnus Damm
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/cpumask.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/sched.h>
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#include <linux/delay.h>
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#include <linux/cpu.h>
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#include <asm/sections.h>
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#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
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#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
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#define STBCR_MSTP 0x00000001
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#define STBCR_RESET 0x00000002
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#define STBCR_SLEEP 0x00000004
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#define STBCR_LTSLP 0x80000000
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static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
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{
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unsigned int message = (unsigned int)(long)arg;
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unsigned int cpu = hard_smp_processor_id();
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unsigned int offs = 4 * cpu;
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unsigned int x;
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x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
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x &= (1 << (message << 2));
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__raw_writel(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
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smp_message_recv(message);
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return IRQ_HANDLED;
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}
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static void shx3_smp_setup(void)
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{
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unsigned int cpu = 0;
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int i, num;
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init_cpu_possible(cpumask_of(cpu));
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/* Enable light sleep for the boot CPU */
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__raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu));
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__cpu_number_map[0] = 0;
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__cpu_logical_map[0] = 0;
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/*
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* Do this stupidly for now.. we don't have an easy way to probe
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* for the total number of cores.
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*/
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for (i = 1, num = 0; i < NR_CPUS; i++) {
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set_cpu_possible(i, true);
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__cpu_number_map[i] = ++num;
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__cpu_logical_map[num] = i;
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}
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printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
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}
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static void shx3_prepare_cpus(unsigned int max_cpus)
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{
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int i;
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BUILD_BUG_ON(SMP_MSG_NR >= 8);
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for (i = 0; i < SMP_MSG_NR; i++)
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request_irq(104 + i, ipi_interrupt_handler,
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IRQF_PERCPU, "IPI", (void *)(long)i);
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for (i = 0; i < max_cpus; i++)
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set_cpu_present(i, true);
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}
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static void shx3_start_cpu(unsigned int cpu, unsigned long entry_point)
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{
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if (__in_29bit_mode())
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__raw_writel(entry_point, RESET_REG(cpu));
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else
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__raw_writel(virt_to_phys(entry_point), RESET_REG(cpu));
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if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
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__raw_writel(STBCR_MSTP, STBCR_REG(cpu));
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while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
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cpu_relax();
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/* Start up secondary processor by sending a reset */
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__raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu));
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}
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static unsigned int shx3_smp_processor_id(void)
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{
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return __raw_readl(0xff000048); /* CPIDR */
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}
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static void shx3_send_ipi(unsigned int cpu, unsigned int message)
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{
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unsigned long addr = 0xfe410070 + (cpu * 4);
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BUG_ON(cpu >= 4);
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__raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
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}
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static void shx3_update_boot_vector(unsigned int cpu)
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{
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__raw_writel(STBCR_MSTP, STBCR_REG(cpu));
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while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
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cpu_relax();
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__raw_writel(STBCR_RESET, STBCR_REG(cpu));
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}
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static int shx3_cpu_prepare(unsigned int cpu)
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{
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shx3_update_boot_vector(cpu);
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return 0;
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}
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static int register_shx3_cpu_notifier(void)
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{
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cpuhp_setup_state_nocalls(CPUHP_SH_SH3X_PREPARE, "sh/shx3:prepare",
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shx3_cpu_prepare, NULL);
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return 0;
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}
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late_initcall(register_shx3_cpu_notifier);
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struct plat_smp_ops shx3_smp_ops = {
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.smp_setup = shx3_smp_setup,
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.prepare_cpus = shx3_prepare_cpus,
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.start_cpu = shx3_start_cpu,
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.smp_processor_id = shx3_smp_processor_id,
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.send_ipi = shx3_send_ipi,
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.cpu_die = native_cpu_die,
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.cpu_disable = native_cpu_disable,
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.play_dead = native_play_dead,
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};
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