212 lines
6 KiB
C
Executable file
212 lines
6 KiB
C
Executable file
#include <linux/efi.h>
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#include <asm/e820/types.h>
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#include <asm/processor.h>
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#include <asm/efi.h>
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#include "pgtable.h"
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#include "../string.h"
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/*
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* __force_order is used by special_insns.h asm code to force instruction
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* serialization.
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*
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* It is not referenced from the code, but GCC < 5 with -fPIE would fail
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* due to an undefined symbol. Define it to make these ancient GCCs work.
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*/
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unsigned long __force_order;
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#define BIOS_START_MIN 0x20000U /* 128K, less than this is insane */
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#define BIOS_START_MAX 0x9f000U /* 640K, absolute maximum */
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struct paging_config {
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unsigned long trampoline_start;
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unsigned long l5_required;
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};
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/* Buffer to preserve trampoline memory */
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static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
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/*
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* Trampoline address will be printed by extract_kernel() for debugging
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* purposes.
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*
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* Avoid putting the pointer into .bss as it will be cleared between
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* paging_prepare() and extract_kernel().
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*/
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unsigned long *trampoline_32bit __section(.data);
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extern struct boot_params *boot_params;
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int cmdline_find_option_bool(const char *option);
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static unsigned long find_trampoline_placement(void)
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{
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unsigned long bios_start = 0, ebda_start = 0;
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unsigned long trampoline_start;
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struct boot_e820_entry *entry;
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char *signature;
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int i;
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/*
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* Find a suitable spot for the trampoline.
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* This code is based on reserve_bios_regions().
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*/
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/*
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* EFI systems may not provide legacy ROM. The memory may not be mapped
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* at all.
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*
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* Only look for values in the legacy ROM for non-EFI system.
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*/
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signature = (char *)&boot_params->efi_info.efi_loader_signature;
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if (strncmp(signature, EFI32_LOADER_SIGNATURE, 4) &&
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strncmp(signature, EFI64_LOADER_SIGNATURE, 4)) {
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ebda_start = *(unsigned short *)0x40e << 4;
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bios_start = *(unsigned short *)0x413 << 10;
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}
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if (bios_start < BIOS_START_MIN || bios_start > BIOS_START_MAX)
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bios_start = BIOS_START_MAX;
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if (ebda_start > BIOS_START_MIN && ebda_start < bios_start)
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bios_start = ebda_start;
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bios_start = round_down(bios_start, PAGE_SIZE);
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/* Find the first usable memory region under bios_start. */
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for (i = boot_params->e820_entries - 1; i >= 0; i--) {
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unsigned long new = bios_start;
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entry = &boot_params->e820_table[i];
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/* Skip all entries above bios_start. */
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if (bios_start <= entry->addr)
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continue;
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/* Skip non-RAM entries. */
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if (entry->type != E820_TYPE_RAM)
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continue;
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/* Adjust bios_start to the end of the entry if needed. */
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if (bios_start > entry->addr + entry->size)
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new = entry->addr + entry->size;
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/* Keep bios_start page-aligned. */
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new = round_down(new, PAGE_SIZE);
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/* Skip the entry if it's too small. */
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if (new - TRAMPOLINE_32BIT_SIZE < entry->addr)
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continue;
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/* Protect against underflow. */
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if (new - TRAMPOLINE_32BIT_SIZE > bios_start)
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break;
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bios_start = new;
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break;
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}
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/* Place the trampoline just below the end of low memory */
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return bios_start - TRAMPOLINE_32BIT_SIZE;
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}
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struct paging_config paging_prepare(void *rmode)
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{
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struct paging_config paging_config = {};
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/* Initialize boot_params. Required for cmdline_find_option_bool(). */
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boot_params = rmode;
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/*
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* Check if LA57 is desired and supported.
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*
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* There are several parts to the check:
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* - if the kernel supports 5-level paging: CONFIG_X86_5LEVEL=y
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* - if user asked to disable 5-level paging: no5lvl in cmdline
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* - if the machine supports 5-level paging:
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* + CPUID leaf 7 is supported
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* + the leaf has the feature bit set
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*
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* That's substitute for boot_cpu_has() in early boot code.
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*/
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if (IS_ENABLED(CONFIG_X86_5LEVEL) &&
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!cmdline_find_option_bool("no5lvl") &&
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native_cpuid_eax(0) >= 7 &&
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(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) {
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paging_config.l5_required = 1;
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}
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paging_config.trampoline_start = find_trampoline_placement();
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trampoline_32bit = (unsigned long *)paging_config.trampoline_start;
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/* Preserve trampoline memory */
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memcpy(trampoline_save, trampoline_32bit, TRAMPOLINE_32BIT_SIZE);
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/* Clear trampoline memory first */
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memset(trampoline_32bit, 0, TRAMPOLINE_32BIT_SIZE);
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/* Copy trampoline code in place */
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memcpy(trampoline_32bit + TRAMPOLINE_32BIT_CODE_OFFSET / sizeof(unsigned long),
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&trampoline_32bit_src, TRAMPOLINE_32BIT_CODE_SIZE);
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/*
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* The code below prepares page table in trampoline memory.
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*
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* The new page table will be used by trampoline code for switching
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* from 4- to 5-level paging or vice versa.
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*
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* If switching is not required, the page table is unused: trampoline
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* code wouldn't touch CR3.
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*/
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/*
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* We are not going to use the page table in trampoline memory if we
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* are already in the desired paging mode.
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*/
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if (paging_config.l5_required == !!(native_read_cr4() & X86_CR4_LA57))
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goto out;
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if (paging_config.l5_required) {
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/*
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* For 4- to 5-level paging transition, set up current CR3 as
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* the first and the only entry in a new top-level page table.
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*/
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trampoline_32bit[TRAMPOLINE_32BIT_PGTABLE_OFFSET] = __native_read_cr3() | _PAGE_TABLE_NOENC;
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} else {
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unsigned long src;
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/*
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* For 5- to 4-level paging transition, copy page table pointed
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* by first entry in the current top-level page table as our
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* new top-level page table.
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*
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* We cannot just point to the page table from trampoline as it
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* may be above 4G.
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*/
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src = *(unsigned long *)__native_read_cr3() & PAGE_MASK;
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memcpy(trampoline_32bit + TRAMPOLINE_32BIT_PGTABLE_OFFSET / sizeof(unsigned long),
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(void *)src, PAGE_SIZE);
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}
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out:
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return paging_config;
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}
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void cleanup_trampoline(void *pgtable)
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{
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void *trampoline_pgtable;
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trampoline_pgtable = trampoline_32bit + TRAMPOLINE_32BIT_PGTABLE_OFFSET / sizeof(unsigned long);
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/*
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* Move the top level page table out of trampoline memory,
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* if it's there.
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*/
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if ((void *)__native_read_cr3() == trampoline_pgtable) {
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memcpy(pgtable, trampoline_pgtable, PAGE_SIZE);
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native_write_cr3((unsigned long)pgtable);
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}
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/* Restore trampoline memory */
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memcpy(trampoline_32bit, trampoline_save, TRAMPOLINE_32BIT_SIZE);
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}
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