171 lines
3.7 KiB
C
Executable file
171 lines
3.7 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Pierre Lee <pierre.lee@mediatek.com>
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*/
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#ifndef __DRV_CLK_FHCTL_H
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#define __DRV_CLK_FHCTL_H
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/bitops.h>
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/************************************************
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********** register field **********
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************************************************/
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// REG_CFG mask
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#define MASK_FRDDSX_DYS GENMASK(23, 20)
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#define MASK_FRDDSX_DTS GENMASK(19, 16)
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#define FH_FHCTLX_CFG_PAUSE BIT(4)
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#define FH_SFSTRX_EN BIT(2)
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#define FH_FRDDSX_EN BIT(1)
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#define FH_FHCTLX_EN BIT(0)
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//REG_DDS mask
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#define FH_FHCTLX_PLL_TGL_ORG BIT(31)
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//FHCTLX_DVFS mask
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#define FH_FHCTLX_PLL_DVFS_TRI BIT(31)
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//XXPLL_CON1 mask (APMIXED)
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#define FH_XXPLL_CON1_PCWCHG BIT(31)
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// Default DT/DF valude
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#define REG_CFG_DT_VAL 0x0
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#define REG_CFG_DF_VAL 0x9
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#define REG_HP_EN_APMIXEDSYS_CTR 0
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#define REG_HP_EN_FHCTL_CTR 1
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#define fh_set_field(reg, field, val) \
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do { \
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unsigned int tv = readl(reg); \
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tv &= ~(field); \
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tv |= ((val) << (ffs(field) - 1)); \
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writel(tv, reg); \
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} while (0)
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#define fh_get_field(reg, field, val) \
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do { \
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unsigned int tv = readl(reg); \
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val = ((tv & (field)) >> (ffs(field) - 1)); \
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} while (0)
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struct clk_mt_fhctl_regs {
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/* Common reg */
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void __iomem *reg_unitslope_en;
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void __iomem *reg_hp_en;
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void __iomem *reg_clk_con;
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void __iomem *reg_rst_con;
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void __iomem *reg_slope0;
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void __iomem *reg_slope1;
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/* For PLL specific */
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void __iomem *reg_cfg;
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void __iomem *reg_updnlmt;
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void __iomem *reg_dds;
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void __iomem *reg_dvfs;
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void __iomem *reg_mon;
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void __iomem *reg_con0;
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void __iomem *reg_con1;
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};
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struct clk_mt_fhctl_pll_data {
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const char *pll_name;
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int pll_id;
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int pll_type;
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int pll_default_ssc_rate;
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unsigned int slope0_value;
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unsigned int slope1_value;
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unsigned int dds_mask;
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unsigned int *hp_tbl;
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unsigned int hp_tbl_size;
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unsigned int dds_max; // for UT dds max value.
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unsigned int dds_min; // for UT dds min value.
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};
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struct clk_mt_fhctl {
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struct clk_mt_fhctl_pll_data *pll_data;
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struct clk_mt_fhctl_regs *fh_regs;
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const struct clk_mt_fhctl_hal_ops *hal_ops;
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spinlock_t *lock;
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struct list_head node;
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};
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struct clk_mt_fhctl_hal_ops {
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int (*pll_init)(struct clk_mt_fhctl *fh);
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int (*pll_unpause)(struct clk_mt_fhctl *fh);
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int (*pll_pause)(struct clk_mt_fhctl *fh);
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int (*pll_ssc_disable)(struct clk_mt_fhctl *fh);
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int (*pll_ssc_enable)(struct clk_mt_fhctl *fh, int rate);
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int (*pll_hopping)(struct clk_mt_fhctl *fh,
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unsigned int new_dds, int postdiv);
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};
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struct mtk_fhctl {
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struct device *dev;
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/* set in fhctl probe */
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void __iomem *fhctl_base;
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void __iomem *apmixed_base;
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unsigned int pll_num;
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int *idmap;
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struct clk_mt_fhctl **fh_tbl;
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const struct mtk_fhctl_compatible *dev_comp;
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#if defined(CONFIG_DEBUG_FS)
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struct dentry *debugfs_root;
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#endif
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};
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struct mtk_fhctl_compatible {
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const u16 *common_regs;
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const u16 *pll_regs;
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const u16 *pll_con0_regs;
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const char * const *pll_names;
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unsigned int pll_num;
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unsigned int pll_dds_reg_field_size;
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unsigned int pll_slope0_reg_setting;
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unsigned int pll_slope1_reg_setting;
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};
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enum FHCTL_COMMON_REGS_OFFSET {
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OFFSET_UNITSLOPE_EN,
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OFFSET_HP_EN,
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OFFSET_CLK_CON,
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OFFSET_RST_CON,
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OFFSET_SLOPE0,
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OFFSET_SLOPE1,
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OFFSET_FHCTL_DSSC_CFG,
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};
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enum FHCTL_PLL_REGS_OFFSET {
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OFFSET_CFG,
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OFFSET_UPDNLMT,
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OFFSET_DDS,
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OFFSET_DVFS,
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OFFSET_MON,
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OFFSET_CON0,
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OFFSET_CON1,
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};
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enum FHCTL_PLL_TYPE {
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FH_PLL_TYPE_NOT_SUPPORT,
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FH_PLL_TYPE_GENERAL,
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FH_PLL_TYPE_CPU,
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FH_PLL_TYPE_FORCE,
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};
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struct clk_mt_fhctl *mtk_fh_get_fh_obj_tbl(struct mtk_fhctl *fhctl, int posi);
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extern const struct clk_mt_fhctl_hal_ops mt_fhctl_hal_ops;
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#endif /* __DRV_CLK_FHCTL_H */
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