204 lines
5.6 KiB
C
Executable file
204 lines
5.6 KiB
C
Executable file
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6853-clk.h>
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#define MT_CLKMGR_MODULE_INIT 0
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#define MT_CCF_BRINGUP 1
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#define INV_OFS -1
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/* get spm power status struct to register inside clk_data */
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static struct pwr_status pwr_stat = GATE_PWR_STAT(0x16C,
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0x170, INV_OFS, BIT(21), BIT(21));
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static const struct mtk_gate_regs audsys0_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x0,
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.sta_ofs = 0x0,
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};
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static const struct mtk_gate_regs audsys1_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x4,
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.sta_ofs = 0x4,
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};
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static const struct mtk_gate_regs audsys2_cg_regs = {
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.set_ofs = 0x8,
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.clr_ofs = 0x8,
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.sta_ofs = 0x8,
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};
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#define GATE_AUDSYS0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &audsys0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr, \
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.pwr_stat = &pwr_stat, \
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}
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#define GATE_AUDSYS1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &audsys1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr, \
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.pwr_stat = &pwr_stat, \
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}
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#define GATE_AUDSYS2(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &audsys2_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr, \
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.pwr_stat = &pwr_stat, \
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}
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static const struct mtk_gate audsys_clks[] = {
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/* AUDSYS0 */
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GATE_AUDSYS0(CLK_AUDSYS_AFE, "aud_afe",
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"audio_ck"/* parent */, 2),
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GATE_AUDSYS0(CLK_AUDSYS_22M, "aud_22m",
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"aud_engen1_ck"/* parent */, 8),
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GATE_AUDSYS0(CLK_AUDSYS_24M, "aud_24m",
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"aud_engen2_ck"/* parent */, 9),
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GATE_AUDSYS0(CLK_AUDSYS_APLL2_TUNER, "aud_apll2_tuner",
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"aud_engen2_ck"/* parent */, 18),
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GATE_AUDSYS0(CLK_AUDSYS_APLL_TUNER, "aud_apll_tuner",
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"aud_engen1_ck"/* parent */, 19),
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GATE_AUDSYS0(CLK_AUDSYS_TDM, "aud_tdm_ck",
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"aud_1_ck"/* parent */, 20),
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GATE_AUDSYS0(CLK_AUDSYS_ADC, "aud_adc",
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"audio_ck"/* parent */, 24),
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GATE_AUDSYS0(CLK_AUDSYS_DAC, "aud_dac",
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"audio_ck"/* parent */, 25),
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GATE_AUDSYS0(CLK_AUDSYS_DAC_PREDIS, "aud_dac_predis",
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"audio_ck"/* parent */, 26),
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GATE_AUDSYS0(CLK_AUDSYS_TML, "aud_tml",
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"audio_ck"/* parent */, 27),
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GATE_AUDSYS0(CLK_AUDSYS_NLE, "aud_nle",
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"audio_ck"/* parent */, 28),
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/* AUDSYS1 */
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GATE_AUDSYS1(CLK_AUDSYS_I2S1_BCLK, "aud_i2s1_bclk",
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"audio_ck"/* parent */, 4),
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GATE_AUDSYS1(CLK_AUDSYS_I2S2_BCLK, "aud_i2s2_bclk",
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"audio_ck"/* parent */, 5),
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GATE_AUDSYS1(CLK_AUDSYS_I2S3_BCLK, "aud_i2s3_bclk",
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"audio_ck"/* parent */, 6),
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GATE_AUDSYS1(CLK_AUDSYS_I2S4_BCLK, "aud_i2s4_bclk",
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"audio_ck"/* parent */, 7),
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GATE_AUDSYS1(CLK_AUDSYS_CONNSYS_I2S_ASRC, "aud_connsys_i2s_asrc",
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"audio_ck"/* parent */, 12),
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GATE_AUDSYS1(CLK_AUDSYS_GENERAL1_ASRC, "aud_general1_asrc",
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"audio_ck"/* parent */, 13),
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GATE_AUDSYS1(CLK_AUDSYS_GENERAL2_ASRC, "aud_general2_asrc",
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"audio_ck"/* parent */, 14),
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GATE_AUDSYS1(CLK_AUDSYS_DAC_HIRES, "aud_dac_hires",
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"audio_h_ck"/* parent */, 15),
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GATE_AUDSYS1(CLK_AUDSYS_ADC_HIRES, "aud_adc_hires",
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"audio_h_ck"/* parent */, 16),
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GATE_AUDSYS1(CLK_AUDSYS_ADC_HIRES_TML, "aud_adc_hires_tml",
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"audio_h_ck"/* parent */, 17),
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GATE_AUDSYS1(CLK_AUDSYS_ADDA6_ADC, "aud_adda6_adc",
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"audio_ck"/* parent */, 20),
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GATE_AUDSYS1(CLK_AUDSYS_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
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"audio_h_ck"/* parent */, 21),
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GATE_AUDSYS1(CLK_AUDSYS_3RD_DAC, "aud_3rd_dac",
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"audio_ck"/* parent */, 28),
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GATE_AUDSYS1(CLK_AUDSYS_3RD_DAC_PREDIS, "aud_3rd_dac_predis",
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"audio_ck"/* parent */, 29),
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GATE_AUDSYS1(CLK_AUDSYS_3RD_DAC_TML, "aud_3rd_dac_tml",
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"audio_ck"/* parent */, 30),
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GATE_AUDSYS1(CLK_AUDSYS_3RD_DAC_HIRES, "aud_3rd_dac_hires",
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"audio_h_ck"/* parent */, 31),
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/* AUDSYS2 */
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GATE_AUDSYS2(CLK_AUDSYS_I2S5_BCLK, "aud_i2s5_bclk",
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"audio_ck"/* parent */, 0),
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GATE_AUDSYS2(CLK_AUDSYS_I2S6_BCLK, "aud_i2s6_bclk",
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"audio_ck"/* parent */, 1),
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GATE_AUDSYS2(CLK_AUDSYS_I2S7_BCLK, "aud_i2s7_bclk",
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"audio_ck"/* parent */, 2),
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GATE_AUDSYS2(CLK_AUDSYS_I2S8_BCLK, "aud_i2s8_bclk",
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"audio_ck"/* parent */, 3),
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GATE_AUDSYS2(CLK_AUDSYS_I2S9_BCLK, "aud_i2s9_bclk",
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"audio_ck"/* parent */, 4),
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};
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static int clk_mt6853_audsys_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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#if MT_CCF_BRINGUP
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pr_notice("%s init begin\n", __func__);
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#endif
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clk_data = mtk_alloc_clk_data(CLK_AUDSYS_NR_CLK);
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mtk_clk_register_gates(node, audsys_clks, ARRAY_SIZE(audsys_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s init end\n", __func__);
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#endif
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return r;
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}
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static const struct of_device_id of_match_clk_mt6853_audsys[] = {
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{ .compatible = "mediatek,mt6853-audio", },
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{}
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};
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#if MT_CLKMGR_MODULE_INIT
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static struct platform_driver clk_mt6853_audsys_drv = {
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.probe = clk_mt6853_audsys_probe,
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.driver = {
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.name = "clk-mt6853-audsys",
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.of_match_table = of_match_clk_mt6853_audsys,
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},
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};
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builtin_platform_driver(clk_mt6853_audsys_drv);
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#else
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static struct platform_driver clk_mt6853_audsys_drv = {
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.probe = clk_mt6853_audsys_probe,
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.driver = {
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.name = "clk-mt6853-audsys",
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.of_match_table = of_match_clk_mt6853_audsys,
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},
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};
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static int __init clk_mt6853_audsys_platform_init(void)
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{
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return platform_driver_register(&clk_mt6853_audsys_drv);
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}
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arch_initcall(clk_mt6853_audsys_platform_init);
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#endif /* MT_CLKMGR_MODULE_INIT */
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