c05564c4d8
Android 13
378 lines
8.4 KiB
C
Executable file
378 lines
8.4 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6877-clk.h>
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#define MT_CCF_BRINGUP 1
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/* Regular Number Definition */
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#define INV_OFS -1
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#define INV_BIT -1
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static const struct mtk_gate_regs impc_cg_regs = {
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.set_ofs = 0xe08,
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.clr_ofs = 0xe04,
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.sta_ofs = 0xe00,
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};
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#define GATE_IMPC(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &impc_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate impc_clks[] = {
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GATE_IMPC(CLK_IMPC_AP_CLOCK_I2C10, "impc_ap_clock_i2c10",
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"fi2c_pseudo_ck"/* parent */, 0),
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GATE_IMPC(CLK_IMPC_AP_CLOCK_I2C11, "impc_ap_clock_i2c11",
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"fi2c_pseudo_ck"/* parent */, 1),
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};
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static const struct mtk_gate_regs impe_cg_regs = {
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.set_ofs = 0xe08,
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.clr_ofs = 0xe04,
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.sta_ofs = 0xe00,
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};
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#define GATE_IMPE(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &impe_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate impe_clks[] = {
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GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C3, "impe_ap_clock_i2c3",
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"fi2c_pseudo_ck"/* parent */, 0),
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};
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static const struct mtk_gate_regs impn_cg_regs = {
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.set_ofs = 0xe08,
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.clr_ofs = 0xe04,
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.sta_ofs = 0xe00,
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};
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#define GATE_IMPN(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &impn_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate impn_clks[] = {
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GATE_IMPN(CLK_IMPN_AP_CLOCK_I2C6, "impn_ap_clock_i2c6",
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"fi2c_pseudo_ck"/* parent */, 0),
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};
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static const struct mtk_gate_regs imps_cg_regs = {
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.set_ofs = 0xe08,
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.clr_ofs = 0xe04,
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.sta_ofs = 0xe00,
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};
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#define GATE_IMPS(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &imps_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate imps_clks[] = {
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GATE_IMPS(CLK_IMPS_AP_CLOCK_I2C5, "imps_ap_clock_i2c5",
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"fi2c_pseudo_ck"/* parent */, 0),
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GATE_IMPS(CLK_IMPS_AP_CLOCK_I2C7, "imps_ap_clock_i2c7",
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"fi2c_pseudo_ck"/* parent */, 1),
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GATE_IMPS(CLK_IMPS_AP_CLOCK_I2C8, "imps_ap_clock_i2c8",
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"fi2c_pseudo_ck"/* parent */, 2),
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GATE_IMPS(CLK_IMPS_AP_CLOCK_I2C9, "imps_ap_clock_i2c9",
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"fi2c_pseudo_ck"/* parent */, 3),
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};
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static const struct mtk_gate_regs impw_cg_regs = {
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.set_ofs = 0xe08,
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.clr_ofs = 0xe04,
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.sta_ofs = 0xe00,
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};
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#define GATE_IMPW(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &impw_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate impw_clks[] = {
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GATE_IMPW(CLK_IMPW_AP_CLOCK_I2C0, "impw_ap_clock_i2c0",
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"fi2c_pseudo_ck"/* parent */, 0),
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};
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static const struct mtk_gate_regs impws_cg_regs = {
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.set_ofs = 0xe08,
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.clr_ofs = 0xe04,
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.sta_ofs = 0xe00,
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};
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#define GATE_IMPWS(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &impws_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate impws_clks[] = {
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GATE_IMPWS(CLK_IMPWS_AP_CLOCK_I2C1, "impws_ap_clock_i2c1",
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"fi2c_pseudo_ck"/* parent */, 0),
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GATE_IMPWS(CLK_IMPWS_AP_CLOCK_I2C2, "impws_ap_clock_i2c2",
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"fi2c_pseudo_ck"/* parent */, 1),
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GATE_IMPWS(CLK_IMPWS_AP_CLOCK_I2C4, "impws_ap_clock_i2c4",
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"fi2c_pseudo_ck"/* parent */, 2),
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};
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static int clk_mt6877_impc_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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#if MT_CCF_BRINGUP
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pr_notice("%s init begin\n", __func__);
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#endif
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clk_data = mtk_alloc_clk_data(CLK_IMPC_NR_CLK);
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mtk_clk_register_gates(node, impc_clks, ARRAY_SIZE(impc_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s init end\n", __func__);
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#endif
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return r;
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}
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static int clk_mt6877_impe_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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#if MT_CCF_BRINGUP
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pr_notice("%s init begin\n", __func__);
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#endif
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clk_data = mtk_alloc_clk_data(CLK_IMPE_NR_CLK);
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mtk_clk_register_gates(node, impe_clks, ARRAY_SIZE(impe_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s init end\n", __func__);
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#endif
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return r;
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}
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static int clk_mt6877_impn_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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#if MT_CCF_BRINGUP
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pr_notice("%s init begin\n", __func__);
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#endif
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clk_data = mtk_alloc_clk_data(CLK_IMPN_NR_CLK);
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mtk_clk_register_gates(node, impn_clks, ARRAY_SIZE(impn_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s init end\n", __func__);
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#endif
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return r;
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}
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static int clk_mt6877_imps_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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#if MT_CCF_BRINGUP
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pr_notice("%s init begin\n", __func__);
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#endif
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clk_data = mtk_alloc_clk_data(CLK_IMPS_NR_CLK);
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mtk_clk_register_gates(node, imps_clks, ARRAY_SIZE(imps_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s init end\n", __func__);
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#endif
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return r;
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}
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static int clk_mt6877_impw_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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#if MT_CCF_BRINGUP
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pr_notice("%s init begin\n", __func__);
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#endif
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clk_data = mtk_alloc_clk_data(CLK_IMPW_NR_CLK);
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mtk_clk_register_gates(node, impw_clks, ARRAY_SIZE(impw_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s init end\n", __func__);
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#endif
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return r;
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}
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static int clk_mt6877_impws_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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#if MT_CCF_BRINGUP
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pr_notice("%s init begin\n", __func__);
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#endif
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clk_data = mtk_alloc_clk_data(CLK_IMPWS_NR_CLK);
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mtk_clk_register_gates(node, impws_clks, ARRAY_SIZE(impws_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s init end\n", __func__);
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#endif
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return r;
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}
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static const struct of_device_id of_match_clk_mt6877_i2c[] = {
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{
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.compatible = "mediatek,mt6877-imp_iic_wrap_c",
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.data = clk_mt6877_impc_probe,
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}, {
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.compatible = "mediatek,mt6877-imp_iic_wrap_e",
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.data = clk_mt6877_impe_probe,
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}, {
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.compatible = "mediatek,mt6877-imp_iic_wrap_n",
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.data = clk_mt6877_impn_probe,
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}, {
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.compatible = "mediatek,mt6877-imp_iic_wrap_s",
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.data = clk_mt6877_imps_probe,
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}, {
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.compatible = "mediatek,mt6877-imp_iic_wrap_w",
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.data = clk_mt6877_impw_probe,
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}, {
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.compatible = "mediatek,mt6877-imp_iic_wrap_ws",
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.data = clk_mt6877_impws_probe,
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}, {
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/* sentinel */
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}
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};
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static int clk_mt6877_i2c_probe(struct platform_device *pdev)
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{
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int (*clk_probe)(struct platform_device *pd);
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int r;
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clk_probe = of_device_get_match_data(&pdev->dev);
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if (!clk_probe)
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return -EINVAL;
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r = clk_probe(pdev);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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return r;
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}
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static struct platform_driver clk_mt6877_i2c_drv = {
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.probe = clk_mt6877_i2c_probe,
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.driver = {
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.name = "clk-mt6877-i2c",
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.of_match_table = of_match_clk_mt6877_i2c,
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},
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};
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static int __init clk_mt6877_i2c_init(void)
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{
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return platform_driver_register(&clk_mt6877_i2c_drv);
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}
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arch_initcall(clk_mt6877_i2c_init);
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