152 lines
4.1 KiB
C
Executable file
152 lines
4.1 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Owen Chen <owen.chen@mediatek.com>
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*/
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#ifndef _CLK_MT6893_FMETER_H
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#define _CLK_MT6893_FMETER_H
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/* generate from clock_table.xlsx from TOPCKGEN DE */
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/* CKGEN Part */
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#define FM_AXI_CK 1
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#define FM_SPM_CK 2
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#define FM_SCP_CK 3
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#define FM_BUS_CK 4
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#define FM_DISP_CK 5
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#define FM_MDP_CK 6
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#define FM_IMG1_CK 7
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#define FM_IMG2_CK 8
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#define FM_IPE_CK 9
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#define FM_DPE_CK 10
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#define FM_MM_CK 11
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#define FM_CCU_CK 12
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#define FM_DSP_CK 13
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#define FM_DSP1_CK 14
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#define FM_DSP2_CK 15
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#define FM_DSP3_CK 16
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#define FM_DSP4_CK 17
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#define FM_DSP5_CK 18
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#define FM_DSP6_CK 19
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#define FM_DSP7_CK 20
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#define FM_IPU_IF_CK 21
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#define FM_MFG_REF_CK 22
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#define FM_FCAMTG_CK 23
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#define FM_FCAMTG2_CK 24
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#define FM_FCAMTG3_CK 25
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#define FM_FCAMTG4_CK 26
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#define FM_FUART_CK 27
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#define FM_SPI_CK 28
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#define FM_MSDC50_0_H_CK 29
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#define FM_MSDC50_0_CK 30
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#define FM_MSDC30_1_CK 31
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#define FM_AUDIO_CK 32
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#define FM_AUD_INTBUS_CK 33
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#define FM_FPWRAP_ULPOSC_CK 34
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#define FM_ATB_CK 35
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#define FM_SSPM_CK 36
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#define FM_DP_CK 37
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#define FM_SCAM_CK 38
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#define FM_FDISP_PWM_CK 39
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#define FM_FUSB_CK 40
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#define FM_FSSUSB_XHCI_CK 41
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#define FM_I2C_CK 42
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#define FM_FSENINF_CK 43
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#define FM_MCUPM_CK 44
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#define FM_SPMI_MST_CK 45
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#define FM_DVFSRC_CK 46
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#define FM_DXCC_CK 47
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#define FM_AUD_ENGEN1_CK 48
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#define FM_AUD_ENGEN2_CK 49
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#define FM_AES_UFSFDE_CK 50
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#define FM_UFS_CK 51
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#define FM_AUD_1_CK 52
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#define FM_AUD_2_CK 53
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#define FM_ADSP_CK 54
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#define FM_DPMAIF_MAIN_CK 55
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#define FM_VENC_CK 56
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#define FM_VDEC_CK 57
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#define FM_VDEC_LAT_CK 58
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#define FM_CAMTM_CK 59
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#define FM_PWM_CK 60
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#define FM_AUDIO_H_CK 61
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#define FM_FCAMTG5_CK 62
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#define FM_FCAMTG6_CK 63
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/* ABIST Part */
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#define FM_ADSPPLL_CK 1
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#define FM_APLL1_CK 2
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#define FM_APLL2_CK 3
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#define FM_APPLLGP_MON_FM_CK 4
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#define FM_APUPLL_D2_CK 5
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#define FM_ARMPLL_BL0_CK 6
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#define FM_ARMPLL_BL1_CK 7
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#define FM_ARMPLL_BL2_CK 8
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#define FM_ARMPLL_BL3_CK 9
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#define FM_ARMPLL_LL_CK 10
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#define FM_CCIPLL_CK 11
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#define FM_CSI0A_CDPHY_DELAYCAL_CK 12
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#define FM_CSI0B_CDPHY_DELAYCAL_CK 13
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#define FM_CSI1A_DPHY_DELAYCAL_CK 14
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#define FM_CSI1B_DPHY_DELAYCAL_CK 15
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#define FM_CSI2A_DPHY_DELAYCAL_CK 16
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#define FM_CSI2B_DPHY_DELAYCAL_CK 17
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#define FM_CSI3A_DPHY_DELAYCAL_CK 18
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#define FM_CSI3B_DPHY_DELAYCAL_CK 19
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#define FM_DSI0_LNTC_DSICLK 20
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#define FM_DSI0_MPPLL_TST_CK 21
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#define FM_DSI1_LNTC_DSICLK 22
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#define FM_DSI1_MPPLL_TST_CK 23
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#define FM_MAINPLL_CK 24
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#define FM_MDPLL1_FS26M_GUIDE 25
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#define FM_MFGPLL_CK 26
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#define FM_MMPLL_CK 27
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#define FM_MMPLL_D3_CK 28
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#define FM_MPLL_CK 29
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#define FM_MSDCPLL_CK 30
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#define FM_RCLRPLL_DIV4_CH02 31
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#define FM_RCLRPLL_DIV4_CH13 32
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#define FM_RPHYPLL_DIV4_CH02 33
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#define FM_RPHYPLL_DIV4_CH13 34
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#define FM_TVDPLL_CK 35
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#define FM_ULPOSC2_CK 36
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#define FM_ULPOSC_CK 37
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#define FM_UNIVPLL_CK 38
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#define FM_USB20_192M_CK 39
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#define FM_MPLL_52M_DIV 40
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#define FM_UFS_MP_CLK2FREQ 41
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#define FM_WBG_DIG_BPLL_CK 42
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#define FM_WBG_DIG_WPLL_CK960 43
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#define FMEM_AFT_CH0 44
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#define FMEM_AFT_CH1 45
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#define FMEM_AFT_CH2 46
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#define FMEM_AFT_CH3 47
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#define FMEM_BFE_CH0 48
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#define FMEM_BFE_CH1 49
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#define FM_466M_FMEM_INFRASYS 50
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#define FM_MCUSYS_ARM_OUT_ALL 51
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#define FM_MSDC01_IN_CK 52
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#define FM_MSDC02_IN_CK 53
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#define FM_MSDC11_IN_CK 54
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#define FM_MSDC12_IN_CK 55
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#define FM_MSDC21_IN_CK 56
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#define FM_MSDC22_IN_CK 57
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#define FM_RTC32K_I_VAO 58
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#define FM_CKOMO1_CK 60
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#define FM_CKMON2_CK 61
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#define FM_CKMON3_CK 62
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#define FM_CKMON4_CK 63
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enum fm_sys_id {
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FM_GPU_PLL_CTRL = 0,
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FM_APU_PLL_CTRL = 1,
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FM_SYS_NUM = 2,
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};
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extern const struct fmeter_clk *get_fmeter_clks(void);
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extern unsigned int mt_get_abist_freq(unsigned int ID);
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extern unsigned int mt_get_abist2_freq(unsigned int ID);
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extern unsigned int mt_get_ckgen_freq(unsigned int ID);
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#endif /* _CLK_MT6893_FMETER_H */
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