270 lines
7.6 KiB
C
Executable file
270 lines
7.6 KiB
C
Executable file
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Owen Chen <owen.chen@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6893-clk.h>
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#define MT_CCF_BRINGUP 1
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/* Regular Number Definition */
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#define INV_OFS -1
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#define INV_BIT -1
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/* get spm power status struct to register inside clk_data */
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static struct pwr_status mm_pwr_stat = GATE_PWR_STAT(0x16C,
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0x170, INV_OFS, BIT(20), BIT(20));
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static const struct mtk_gate_regs mm0_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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static const struct mtk_gate_regs mm1_cg_regs = {
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.set_ofs = 0x114,
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.clr_ofs = 0x118,
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.sta_ofs = 0x110,
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};
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static const struct mtk_gate_regs mm2_cg_regs = {
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.set_ofs = 0x1a4,
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.clr_ofs = 0x1a8,
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.sta_ofs = 0x1a0,
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};
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#define GATE_MM0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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.pwr_stat = &mm_pwr_stat, \
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}
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#define GATE_MM1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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.pwr_stat = &mm_pwr_stat, \
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}
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#define GATE_MM2(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm2_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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.pwr_stat = &mm_pwr_stat, \
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}
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#define GATE_MM0_IGNORED(_id, _name, _parent, _shift) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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.pwr_stat = &mm_pwr_stat, \
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.flags = CLK_IGNORE_UNUSED, \
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}
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#define GATE_DUMMY1(_id, _name, _parent, _shift) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_dummy, \
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.pwr_stat = &mm_pwr_stat, \
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}
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static const struct mtk_gate mm_clks[] = {
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/* MM0 */
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GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0",
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"disp_ck"/* parent */, 0),
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GATE_MM0(CLK_MM_DISP_RSZ1, "mm_disp_rsz1",
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"disp_ck"/* parent */, 1),
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GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0",
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"disp_ck"/* parent */, 2),
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GATE_MM0(CLK_MM_INLINE, "mm_inline",
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"disp_ck"/* parent */, 3),
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GATE_MM0(CLK_MM_MDP_TDSHP4, "mm_mdp_tdshp4",
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"disp_ck"/* parent */, 4),
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GATE_MM0(CLK_MM_MDP_TDSHP5, "mm_mdp_tdshp5",
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"disp_ck"/* parent */, 5),
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GATE_MM0_IGNORED(CLK_MM_MDP_AAL4, "mm_mdp_aal4",
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"disp_ck"/* parent */, 6),
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GATE_MM0_IGNORED(CLK_MM_MDP_AAL5, "mm_mdp_aal5",
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"disp_ck"/* parent */, 7),
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GATE_MM0(CLK_MM_MDP_HDR4, "mm_mdp_hdr4",
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"disp_ck"/* parent */, 8),
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GATE_MM0(CLK_MM_MDP_HDR5, "mm_mdp_hdr5",
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"disp_ck"/* parent */, 9),
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GATE_MM0(CLK_MM_MDP_RSZ4, "mm_mdp_rsz4",
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"disp_ck"/* parent */, 10),
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GATE_MM0(CLK_MM_MDP_RSZ5, "mm_mdp_rsz5",
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"disp_ck"/* parent */, 11),
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GATE_MM0(CLK_MM_MDP_RDMA4, "mm_mdp_rdma4",
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"disp_ck"/* parent */, 12),
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GATE_MM0(CLK_MM_MDP_RDMA5, "mm_mdp_rdma5",
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"disp_ck"/* parent */, 13),
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GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0",
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"disp_ck"/* parent */, 14),
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GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1",
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"disp_ck"/* parent */, 15),
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GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l",
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"disp_ck"/* parent */, 16),
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GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l",
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"disp_ck"/* parent */, 17),
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GATE_MM0(CLK_MM_DISP_OVL2_2L, "mm_disp_ovl2_2l",
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"disp_ck"/* parent */, 18),
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GATE_MM0(CLK_MM_DISP_MUTEX, "mm_disp_mutex",
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"disp_ck"/* parent */, 19),
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GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1",
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"disp_ck"/* parent */, 20),
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GATE_MM0(CLK_MM_DISP_OVL3_2L, "mm_disp_ovl3_2l",
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"disp_ck"/* parent */, 21),
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GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0",
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"disp_ck"/* parent */, 22),
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GATE_MM0(CLK_MM_DISP_CCORR1, "mm_disp_ccorr1",
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"disp_ck"/* parent */, 23),
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GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0",
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"disp_ck"/* parent */, 24),
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GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1",
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"disp_ck"/* parent */, 25),
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GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0",
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"disp_ck"/* parent */, 26),
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GATE_MM0(CLK_MM_DISP_POSTMASK1, "mm_disp_postmask1",
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"disp_ck"/* parent */, 27),
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GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0",
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"disp_ck"/* parent */, 28),
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GATE_MM0(CLK_MM_DISP_DITHER1, "mm_disp_dither1",
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"disp_ck"/* parent */, 29),
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GATE_MM0(CLK_MM_DSI0_MM_CLK, "mm_dsi0_mm_clk",
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"disp_ck"/* parent */, 30),
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GATE_MM0(CLK_MM_DSI1_MM_CLK, "mm_dsi1_mm_clk",
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"disp_ck"/* parent */, 31),
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/* MM1 */
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GATE_MM1(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0",
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"disp_ck"/* parent */, 0),
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GATE_MM1(CLK_MM_DISP_GAMMA1, "mm_disp_gamma1",
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"disp_ck"/* parent */, 1),
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GATE_MM1(CLK_MM_DISP_AAL0, "mm_disp_aal0",
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"disp_ck"/* parent */, 2),
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GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1",
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"disp_ck"/* parent */, 3),
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GATE_MM1(CLK_MM_DISP_WDMA0, "mm_disp_wdma0",
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"disp_ck"/* parent */, 4),
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GATE_MM1(CLK_MM_DISP_WDMA1, "mm_disp_wdma1",
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"disp_ck"/* parent */, 5),
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GATE_MM1(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0",
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"disp_ck"/* parent */, 6),
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GATE_MM1(CLK_MM_DISP_UFBC_WDMA1, "mm_disp_ufbc_wdma1",
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"disp_ck"/* parent */, 7),
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GATE_MM1(CLK_MM_DISP_RDMA0, "mm_disp_rdma0",
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"disp_ck"/* parent */, 8),
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GATE_MM1(CLK_MM_DISP_RDMA1, "mm_disp_rdma1",
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"disp_ck"/* parent */, 9),
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GATE_MM1(CLK_MM_DISP_RDMA4, "mm_disp_rdma4",
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"disp_ck"/* parent */, 10),
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GATE_MM1(CLK_MM_DISP_RDMA5, "mm_disp_rdma5",
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"disp_ck"/* parent */, 11),
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GATE_MM1(CLK_MM_DISP_DSC_WRAP, "mm_disp_dsc_wrap",
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"disp_ck"/* parent */, 12),
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GATE_MM1(CLK_MM_DP_INTF_MM_CLK, "mm_dp_intf_mm_clk",
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"disp_ck"/* parent */, 13),
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GATE_MM1(CLK_MM_DISP_MERGE0, "mm_disp_merge0",
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"disp_ck"/* parent */, 14),
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GATE_MM1(CLK_MM_DISP_MERGE1, "mm_disp_merge1",
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"disp_ck"/* parent */, 15),
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GATE_DUMMY1(CLK_MM_SMI_COMMON, "mm_smi_common",
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"disp_ck"/* parent */, 19),
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GATE_DUMMY1(CLK_MM_SMI_GALS, "mm_smi_gals",
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"disp_ck"/* parent */, 23),
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GATE_DUMMY1(CLK_MM_SMI_INFRA, "mm_smi_infra",
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"disp_ck"/* parent */, 27),
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GATE_DUMMY1(CLK_MM_SMI_IOMMU, "mm_smi_iommu",
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"disp_ck"/* parent */, 31),
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/* MM2 */
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GATE_MM2(CLK_MM_DSI0_INTF_CLK, "mm_dsi0_intf_clk",
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"disp_ck"/* parent */, 0),
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GATE_MM2(CLK_MM_DSI1_INTF_CLK, "mm_dsi1_intf_clk",
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"disp_ck"/* parent */, 8),
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GATE_MM2(CLK_MM_DP_INTF_INTF_CLK, "mm_dp_intf_intf_clk",
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"dp_ck"/* parent */, 16),
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GATE_MM2(CLK_MM_CK_26_MHZ, "mm_26_mhz",
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"f26m_ck"/* parent */, 24),
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GATE_MM2(CLK_MM_CK_32_KHZ, "mm_32_khz",
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"frtc_ck"/* parent */, 25),
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};
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static const struct mtk_clk_desc mm_mcd = {
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.clks = mm_clks,
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.num_clks = CLK_MM_NR_CLK,
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};
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static int clk_mt6893_mm_probe(struct platform_device *pdev)
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{
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int r;
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#if MT_CCF_BRINGUP
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pr_notice("%s init begin\n", __func__);
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#endif
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r = mtk_clk_simple_probe(pdev);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s init end\n", __func__);
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#endif
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return r;
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}
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static const struct of_device_id of_match_clk_mt6893_mm[] = {
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{
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.compatible = "mediatek,mt6893-mmsys",
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.data = &mm_mcd,
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},
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{}
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};
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static struct platform_driver clk_mt6893_mm_drv = {
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.probe = clk_mt6893_mm_probe,
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.driver = {
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.name = "clk-mt6893-mm",
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.of_match_table = of_match_clk_mt6893_mm,
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},
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};
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static int __init clk_mt6893_mm_init(void)
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{
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return platform_driver_register(&clk_mt6893_mm_drv);
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}
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static void __exit clk_mt6893_mm_exit(void)
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{
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platform_driver_unregister(&clk_mt6893_mm_drv);
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}
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postcore_initcall(clk_mt6893_mm_init);
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module_exit(clk_mt6893_mm_exit);
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MODULE_LICENSE("GPL");
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