1046 lines
18 KiB
C
Executable file
1046 lines
18 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/clk-provider.h>
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#include <linux/syscore_ops.h>
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#include <linux/version.h>
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#include <mt-plat/aee.h>
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#include "clk-mt6833-pg.h"
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#include "clkdbg-mt6833.h"
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#define TAG "[clkchk] "
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#define BUG_ON_CHK_ENABLE 0
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const char * const *get_mt6833_all_clk_names(void)
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{
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static const char * const clks[] = {
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/* apmixedsys */
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"armpll_ll",
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"armpll_bl0",
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"ccipll",
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"mpll",
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"mainpll",
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"univpll",
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"msdcpll",
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"mmpll",
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"adsppll",
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"mfgpll",
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"tvdpll",
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"apll1",
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"apll2",
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"npupll",
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"usbpll",
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/* apmixedsys */
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"mipic0",
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"mipic1",
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"mipid0",
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/* topckgen */
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"axi_sel",
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"spm_sel",
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"scp_sel",
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"bus_aximem_sel",
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"disp_sel",
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"mdp_sel",
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"img1_sel",
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"img2_sel",
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"ipe_sel",
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"dpe_sel",
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"cam_sel",
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"ccu_sel",
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"dsp_sel",
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"dsp1_sel",
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"dsp1_npupll_sel",
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"dsp2_sel",
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"dsp2_npupll_sel",
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"ipu_if_sel",
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"mfg_ref_sel",
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"mfg_pll_sel",
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"camtg_sel",
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"camtg2_sel",
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"camtg3_sel",
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"camtg4_sel",
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"camtg5_sel",
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"uart_sel",
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"spi_sel",
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"msdc50_0_h_sel",
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"msdc50_0_sel",
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"msdc30_1_sel",
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"audio_sel",
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"aud_intbus_sel",
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"pwrap_ulposc_sel",
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"atb_sel",
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"sspm_sel",
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"scam_sel",
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"disp_pwm_sel",
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"usb_sel",
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"ssusb_xhci_sel",
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"i2c_sel",
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"seninf_sel",
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"seninf1_sel",
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"seninf2_sel",
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"dxcc_sel",
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"aud_engen1_sel",
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"aud_engen2_sel",
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"aes_ufsfde_sel",
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"ufs_sel",
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"aud_1_sel",
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"aud_2_sel",
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"adsp_sel",
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"dpmaif_main_sel",
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"venc_sel",
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"vdec_sel",
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"camtm_sel",
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"pwm_sel",
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"audio_h_sel",
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"spmi_mst_sel",
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"dvfsrc_sel",
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"aes_msdcfde_sel",
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"mcupm_sel",
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"sflash_sel",
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"apll_i2s0_mck_sel",
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"apll_i2s1_mck_sel",
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"apll_i2s2_mck_sel",
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"apll_i2s3_mck_sel",
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"apll_i2s4_mck_sel",
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"apll_i2s5_mck_sel",
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"apll_i2s6_mck_sel",
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"apll_i2s7_mck_sel",
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"apll_i2s8_mck_sel",
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"apll_i2s9_mck_sel",
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/* topckgen */
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"apll12_div0",
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"apll12_div1",
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"apll12_div2",
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"apll12_div3",
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"apll12_div4",
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"apll12_divb",
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"apll12_div5",
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"apll12_div6",
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"apll12_div7",
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"apll12_div8",
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"apll12_div9",
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/* infracfg_ao */
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"ifrao_infra_force",
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"ifrao_pmic_tmr",
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"ifrao_pmic_ap",
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"ifrao_pmic_md",
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"ifrao_pmic_conn",
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"ifrao_sej",
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"ifrao_apxgpt",
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"ifrao_gce",
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"ifrao_gce2",
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"ifrao_therm",
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"ifrao_i2c0",
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"ifrao_i2c1",
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"ifrao_i2c2",
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"ifrao_i2c3",
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"ifrao_pwm_hclk",
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"ifrao_pwm1",
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"ifrao_pwm2",
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"ifrao_pwm3",
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"ifrao_pwm4",
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"ifrao_pwm",
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"ifrao_uart0",
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"ifrao_uart1",
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"ifrao_uart2",
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"ifrao_uart3",
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"ifrao_gce_26m",
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"ifrao_dma",
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"ifrao_btif",
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"ifrao_spi0",
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"ifrao_msdc0",
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"ifrao_msdc1",
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"ifrao_msdc0_clk",
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"ifrao_dvfsrc",
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"ifrao_trng",
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"ifrao_auxadc",
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"ifrao_cpum",
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"ifrao_ccif1_ap",
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"ifrao_ccif1_md",
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"ifrao_auxadc_md",
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"ifrao_pcie_tl_26m",
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"ifrao_msdc1_clk",
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"ifrao_msdc0_aes_clk",
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"ifrao_pcie_tl_96m",
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"ifrao_pcie_pl_p_250m",
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"ifrao_dapc",
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"ifrao_ccif_ap",
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"ifrao_debugsys",
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"ifrao_audio",
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"ifrao_ccif_md",
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"ifrao_secore",
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"ifrao_dxcc_ao",
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"ifrao_dbg_trace",
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"ifrao_dramc26",
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"ifrao_ssusb",
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"ifrao_disp_pwm",
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"ifrao_cldmabclk",
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"ifrao_audio26m",
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"ifrao_mdtemp",
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"ifrao_spi1",
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"ifrao_i2c4",
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"ifrao_spi2",
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"ifrao_spi3",
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"ifrao_unipro_sysclk",
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"ifrao_unipro_tick",
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"ifrao_ufs_bclk",
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"ifrao_fsspm",
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"ifrao_sspm_hclk",
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"ifrao_i2c5",
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"ifrao_i2c5a",
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"ifrao_i2c5_imm",
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"ifrao_i2c1a",
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"ifrao_i2c1_imm",
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"ifrao_i2c2a",
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"ifrao_i2c2_imm",
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"ifrao_spi4",
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"ifrao_spi5",
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"ifrao_cq_dma",
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"ifrao_ufs",
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"ifrao_aes",
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"ifrao_ufs_tick",
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"ifrao_ssusb_xhci",
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"ifrao_msdc0sf",
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"ifrao_msdc1sf",
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"ifrao_msdc2sf",
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"ifrao_sspm_26m",
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"ifrao_sspm_32k",
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"ifrao_i2c6",
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"ifrao_ap_msdc0",
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"ifrao_md_msdc0",
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"ifrao_ccif5_ap",
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"ifrao_ccif5_md",
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"ifrao_flashif_h_133m",
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"ifrao_ccif2_ap",
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"ifrao_ccif2_md",
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"ifrao_ccif3_ap",
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"ifrao_ccif3_md",
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"ifrao_sej_f13m",
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"ifrao_i2c7",
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"ifrao_i2c8",
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"ifrao_fbist2fpc",
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"ifrao_dapc_sync",
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"ifrao_dpmaif_main",
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"ifrao_ccif4_ap",
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"ifrao_ccif4_md",
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"ifrao_spi6_ck",
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"ifrao_spi7_ck",
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"ifrao_133m_mclk_ck",
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"ifrao_66m_mclk_ck",
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"ifrao_66m_peri_mclk",
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"ifrao_infra_133m",
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"ifrao_infra_66m",
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"ifrao_peru_bus_133m",
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"ifrao_peru_bus_66m",
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"ifrao_flash_26m",
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"ifrao_sflash_ck",
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"ifrao_ap_dma",
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"ifrao_peri_force",
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/* pericfg */
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"periaxi_disable",
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/* scp */
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"scp_par_adsp_pll",
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/* imp_iic_wrap_c */
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"impc_ap_i2c10",
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"impc_ap_i2c11",
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/* audio */
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"aud_afe",
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"aud_22m",
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"aud_24m",
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"aud_apll2_tuner",
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"aud_apll_tuner",
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"aud_tdm_ck",
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"aud_adc",
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"aud_dac",
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"aud_dac_predis",
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"aud_tml",
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"aud_nle",
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"aud_i2s1_bclk",
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"aud_i2s2_bclk",
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"aud_i2s3_bclk",
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"aud_i2s4_bclk",
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"aud_connsys_i2s_asrc",
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"aud_general1_asrc",
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"aud_general2_asrc",
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"aud_dac_hires",
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"aud_adc_hires",
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"aud_adc_hires_tml",
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"aud_adda6_adc",
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"aud_adda6_adc_hires",
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"aud_3rd_dac",
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"aud_3rd_dac_predis",
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"aud_3rd_dac_tml",
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"aud_3rd_dac_hires",
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"aud_i2s5_bclk",
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"aud_i2s6_bclk",
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"aud_i2s7_bclk",
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"aud_i2s8_bclk",
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"aud_i2s9_bclk",
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/* msdc0sys */
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"msdc0_axi_wrap_cken",
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/* imp_iic_wrap_e */
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"impe_ap_i2c3",
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/* imp_iic_wrap_s */
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"imps_ap_i2c5",
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"imps_ap_i2c7",
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"imps_ap_i2c8",
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"imps_ap_i2c9",
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/* imp_iic_wrap_ws */
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"impws_ap_i2c1",
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"impws_ap_i2c2",
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"impws_ap_i2c4",
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/* imp_iic_wrap_w */
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"impw_ap_i2c6",
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/* imp_iic_wrap_n */
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"impn_ap_i2c0",
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/* mfgsys */
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"mfgcfg_bg3d",
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/* mmsys_config */
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"mm_disp_mutex0",
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"mm_apb_bus",
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"mm_disp_ovl0",
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"mm_disp_rdma0",
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"mm_disp_ovl0_2l",
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"mm_disp_wdma0",
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"mm_disp_ccorr1",
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"mm_disp_rsz0",
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"mm_disp_aal0",
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"mm_disp_ccorr0",
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"mm_disp_color0",
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"mm_smi_infra",
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"mm_disp_dsc_wrap",
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"mm_disp_gamma0",
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"mm_disp_postmask0",
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"mm_disp_spr0",
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"mm_disp_dither0",
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"mm_smi_common",
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"mm_disp_cm0",
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"mm_dsi0",
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"mm_disp_fake_eng0",
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"mm_disp_fake_eng1",
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"mm_smi_gals",
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"mm_smi_iommu",
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/* imgsys1 */
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"imgsys1_larb9",
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"imgsys1_larb10",
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"imgsys1_dip",
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"imgsys1_gals",
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/* imgsys2 */
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"imgsys2_larb9",
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"imgsys2_larb10",
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"imgsys2_mfb",
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"imgsys2_wpe",
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"imgsys2_mss",
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"imgsys2_gals",
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/* vdec_gcon */
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"vdec_larb1_cken",
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"vdec_cken",
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"vdec_active",
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/* venc_gcon */
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"venc_set0_larb",
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"venc_set1_venc",
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"jpgenc",
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"venc_set5_gals",
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/* apu_conn */
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"apuc_apu",
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"apuc_ahb",
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"apuc_axi",
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"apuc_isp",
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"apuc_cam_adl",
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"apuc_img_adl",
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"apuc_emi_26m",
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"apuc_vpu_udi",
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"apuc_edma_0",
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"apuc_edma_1",
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"apuc_edmal_0",
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"apuc_edmal_1",
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"apuc_mnoc",
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"apuc_tcm",
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"apuc_md32",
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"apuc_iommu_0",
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"apuc_md32_32k",
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/* apu_vcore */
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"apuv_ahb",
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"apuv_axi",
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"apuv_adl",
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"apuv_qos",
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/* apu0 */
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"apu0_apu",
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"apu0_axi_m",
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"apu0_jtag",
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"apu0_pclk",
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/* apu1 */
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"apu1_apu",
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"apu1_axi_m",
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"apu1_jtag",
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"apu1_pclk",
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/* camsys_main */
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"cam_m_larb13",
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"cam_m_larb14",
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"cam_m_reserved0",
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"cam_m_cam",
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"cam_m_camtg",
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"cam_m_seninf",
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"cam_m_camsv1",
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"cam_m_camsv2",
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"cam_m_camsv3",
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"cam_m_ccu0",
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"cam_m_ccu1",
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"cam_m_mraw0",
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"cam_m_reserved2",
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"cam_m_fake_eng",
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"cam_m_ccu_gals",
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"cam_m_cam2mm_gals",
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/* camsys_rawa */
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"cam_ra_larbx",
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"cam_ra_cam",
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"cam_ra_camtg",
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/* camsys_rawb */
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"cam_rb_larbx",
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"cam_rb_cam",
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"cam_rb_camtg",
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/* ipesys */
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"ipe_larb19",
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"ipe_larb20",
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"ipe_smi_subcom",
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"ipe_fd",
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"ipe_fe",
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"ipe_rsc",
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"ipe_dpe",
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"ipe_gals",
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/* mdpsys_config */
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"mdp_rdma0",
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"mdp_tdshp0",
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"mdp_img_dl_async0",
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"mdp_img_dl_async1",
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"mdp_rdma1",
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"mdp_tdshp1",
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"mdp_smi0",
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"mdp_apb_bus",
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"mdp_wrot0",
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"mdp_rsz0",
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"mdp_hdr0",
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"mdp_mutex0",
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"mdp_wrot1",
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"mdp_rsz1",
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"mdp_fake_eng0",
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"mdp_aal0",
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"mdp_aal1",
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"mdp_color0",
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"mdp_img_dl_rel0_as0",
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"mdp_img_dl_rel1_as1",
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/* SCPSYS */
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"PG_MD1",
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"PG_CONN",
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"PG_MDP",
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"PG_DIS",
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"PG_MFG0",
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"PG_MFG1",
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"PG_MFG2",
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"PG_MFG3",
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"PG_MFG5",
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"PG_ISP",
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"PG_ISP2",
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"PG_IPE",
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"PG_VDEC",
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"PG_VENC",
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"PG_AUDIO",
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"PG_ADSP",
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"PG_CAM",
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"PG_CAM_RAWA",
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"PG_CAM_RAWB",
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"PG_VPU",
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/* end */
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NULL
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};
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return clks;
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}
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static const char * const off_pll_names[] = {
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"univpll",
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"msdcpll",
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"mmpll",
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"tvdpll",
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"npupll",
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"usbpll",
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NULL
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};
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static const char * const notice_pll_names[] = {
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"adsppll",
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"apll1",
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"apll2",
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NULL
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};
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static const char * const off_mtcmos_names[] = {
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"PG_DIS",
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"PG_MFG0",
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"PG_MFG1",
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"PG_MFG2",
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"PG_MFG3",
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"PG_MFG5",
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"PG_ISP",
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"PG_ISP2",
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"PG_IPE",
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"PG_VDEC",
|
|
"PG_VENC",
|
|
"PG_CAM",
|
|
"PG_CAM_RAWA",
|
|
"PG_CAM_RAWB",
|
|
"PG_VPU",
|
|
NULL
|
|
};
|
|
|
|
static const char * const notice_mtcmos_names[] = {
|
|
"PG_MD1",
|
|
"PG_CONN",
|
|
"PG_ADSP",
|
|
"PG_AUDIO",
|
|
NULL
|
|
};
|
|
|
|
static const char *ccf_state(struct clk_hw *hw)
|
|
{
|
|
if (__clk_get_enable_count(hw->clk))
|
|
return "enabled";
|
|
|
|
if (clk_hw_is_prepared(hw))
|
|
return "prepared";
|
|
|
|
return "disabled";
|
|
}
|
|
|
|
static void print_enabled_clks(void)
|
|
{
|
|
const char * const *cn = get_mt6833_all_clk_names();
|
|
const char *fix_clk = "clk26m";
|
|
|
|
for (; *cn; cn++) {
|
|
int valid = 0;
|
|
struct clk *c = __clk_lookup(*cn);
|
|
struct clk_hw *c_hw = __clk_get_hw(c);
|
|
struct clk_hw *p_hw;
|
|
const char *c_name;
|
|
const char *p_name;
|
|
const char * const *pn;
|
|
|
|
if (IS_ERR_OR_NULL(c) || !c_hw)
|
|
continue;
|
|
|
|
if (!__clk_get_enable_count(c))
|
|
continue;
|
|
|
|
p_hw = clk_hw_get_parent(c_hw);
|
|
c_name = clk_hw_get_name(c_hw);
|
|
p_name = p_hw ? clk_hw_get_name(p_hw) : 0;
|
|
while (p_name && strcmp(p_name, fix_clk)) {
|
|
struct clk_hw *p_hw_temp;
|
|
|
|
p_hw_temp = clk_hw_get_parent(p_hw);
|
|
p_name = p_hw_temp ? clk_hw_get_name(p_hw_temp) : 0;
|
|
if (p_name && strcmp(p_name, fix_clk))
|
|
p_hw = p_hw_temp;
|
|
else if (p_name && !strcmp(p_name, fix_clk)) {
|
|
c_name = clk_hw_get_name(p_hw);
|
|
break;
|
|
}
|
|
}
|
|
for (pn = off_pll_names; *pn && c_name; pn++)
|
|
if (!strncmp(c_name, *pn, 10)) {
|
|
valid++;
|
|
break;
|
|
}
|
|
|
|
if (!valid)
|
|
continue;
|
|
|
|
p_hw = clk_hw_get_parent(c_hw);
|
|
pr_notice("[%-17s: %8s, %3d, %3d, %10ld, %17s]\n",
|
|
clk_hw_get_name(c_hw),
|
|
ccf_state(c_hw),
|
|
clk_hw_is_prepared(c_hw),
|
|
__clk_get_enable_count(c),
|
|
clk_hw_get_rate(c_hw),
|
|
p_hw ? clk_hw_get_name(p_hw) : "- ");
|
|
}
|
|
}
|
|
|
|
static void check_pll_off(void)
|
|
{
|
|
static struct clk *off_plls[ARRAY_SIZE(off_pll_names)];
|
|
|
|
struct clk **c;
|
|
int invalid = 0;
|
|
// char buf[128] = {0};
|
|
// int n = 0;
|
|
|
|
if (!off_plls[0]) {
|
|
const char * const *pn;
|
|
|
|
for (pn = off_pll_names, c = off_plls; *pn; pn++, c++)
|
|
*c = __clk_lookup(*pn);
|
|
}
|
|
|
|
for (c = off_plls; *c; c++) {
|
|
struct clk_hw *c_hw = __clk_get_hw(*c);
|
|
|
|
if (!c_hw)
|
|
continue;
|
|
|
|
if (!clk_hw_is_enabled(c_hw))
|
|
continue;
|
|
|
|
pr_notice("suspend warning[0m: %s is on\n",
|
|
clk_hw_get_name(c_hw));
|
|
|
|
invalid++;
|
|
}
|
|
|
|
if (invalid) {
|
|
print_enabled_clks();
|
|
|
|
|
|
#ifdef CONFIG_MTK_ENG_BUILD
|
|
#if BUG_ON_CHK_ENABLE
|
|
BUG_ON(1);
|
|
#else
|
|
aee_kernel_warning("CCF MT6833",
|
|
"@%s():%d, PLLs are not off\n", __func__, __LINE__);
|
|
WARN_ON(1);
|
|
#endif
|
|
#else
|
|
aee_kernel_warning("CCF MT6833",
|
|
"@%s():%d, PLLs are not off\n", __func__, __LINE__);
|
|
WARN_ON(1);
|
|
#endif
|
|
}
|
|
}
|
|
/*
|
|
static void check_pll_notice(void)
|
|
{
|
|
static struct clk *off_plls[ARRAY_SIZE(notice_pll_names)];
|
|
|
|
struct clk **c;
|
|
int invalid = 0;
|
|
// char buf[128] = {0};
|
|
// int n = 0;
|
|
|
|
if (!off_plls[0]) {
|
|
const char * const *pn;
|
|
|
|
for (pn = notice_pll_names, c = off_plls; *pn; pn++, c++)
|
|
*c = __clk_lookup(*pn);
|
|
}
|
|
|
|
for (c = off_plls; *c; c++) {
|
|
struct clk_hw *c_hw = __clk_get_hw(*c);
|
|
|
|
if (!c_hw)
|
|
continue;
|
|
|
|
if (!clk_hw_is_enabled(c_hw))
|
|
continue;
|
|
|
|
pr_notice("suspend warning[0m: %s is on\n",
|
|
clk_hw_get_name(c_hw));
|
|
|
|
invalid++;
|
|
}
|
|
|
|
if (invalid)
|
|
print_enabled_clks();
|
|
}
|
|
*/
|
|
static void check_mtcmos_off(void)
|
|
{
|
|
static struct clk *off_mtcmos[ARRAY_SIZE(off_mtcmos_names)];
|
|
|
|
struct clk **c;
|
|
int invalid = 0;
|
|
// char buf[128] = {0};
|
|
// int n = 0;
|
|
|
|
if (!off_mtcmos[0]) {
|
|
const char * const *pn;
|
|
|
|
for (pn = off_mtcmos_names, c = off_mtcmos; *pn; pn++, c++)
|
|
*c = __clk_lookup(*pn);
|
|
}
|
|
|
|
for (c = off_mtcmos; *c; c++) {
|
|
struct clk_hw *c_hw = __clk_get_hw(*c);
|
|
|
|
if (!c_hw)
|
|
continue;
|
|
|
|
if (!clk_hw_is_prepared(c_hw) && !clk_hw_is_enabled(c_hw))
|
|
continue;
|
|
|
|
pr_notice("suspend warning[0m: %s is on\n",
|
|
clk_hw_get_name(c_hw));
|
|
|
|
invalid++;
|
|
}
|
|
|
|
if (invalid) {
|
|
#ifdef CONFIG_MTK_ENG_BUILD
|
|
#if BUG_ON_CHK_ENABLE
|
|
BUG_ON(1);
|
|
#else
|
|
aee_kernel_warning("CCF MT6833",
|
|
"@%s():%d, MTCMOSs are not off\n", __func__, __LINE__);
|
|
WARN_ON(1);
|
|
#endif
|
|
#else
|
|
aee_kernel_warning("CCF MT6833",
|
|
"@%s():%d, MTCMOSs are not off\n", __func__, __LINE__);
|
|
WARN_ON(1);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
static void check_mtcmos_notice(void)
|
|
{
|
|
static struct clk *notice_mtcmos[ARRAY_SIZE(notice_mtcmos_names)];
|
|
|
|
struct clk **c;
|
|
// int invalid = 0;
|
|
// char buf[128] = {0};
|
|
// int n = 0;
|
|
|
|
if (!notice_mtcmos[0]) {
|
|
const char * const *pn;
|
|
|
|
for (pn = notice_mtcmos_names, c = notice_mtcmos;
|
|
*pn; pn++, c++)
|
|
*c = __clk_lookup(*pn);
|
|
}
|
|
|
|
for (c = notice_mtcmos; *c; c++) {
|
|
struct clk_hw *c_hw = __clk_get_hw(*c);
|
|
|
|
if (!c_hw)
|
|
continue;
|
|
|
|
if (!clk_hw_is_prepared(c_hw) && !clk_hw_is_enabled(c_hw))
|
|
continue;
|
|
|
|
pr_notice("suspend warning[0m: %s\n", clk_hw_get_name(c_hw));
|
|
}
|
|
}
|
|
|
|
void print_enabled_clks_once(void)
|
|
{
|
|
static bool first_flag = true;
|
|
|
|
if (first_flag) {
|
|
first_flag = false;
|
|
print_enabled_clks();
|
|
}
|
|
}
|
|
|
|
static int clkchk_syscore_suspend(void)
|
|
{
|
|
check_pll_off();
|
|
check_mtcmos_notice();
|
|
check_mtcmos_off();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void clkchk_syscore_resume(void)
|
|
{
|
|
}
|
|
|
|
static struct syscore_ops clkchk_syscore_ops = {
|
|
.suspend = clkchk_syscore_suspend,
|
|
.resume = clkchk_syscore_resume,
|
|
};
|
|
|
|
/*
|
|
* Before MTCMOS off procedure, perform the Subsys CGs sanity check.
|
|
*/
|
|
struct pg_check_swcg {
|
|
struct clk *c;
|
|
const char *name;
|
|
};
|
|
|
|
#define SWCG(_name) { \
|
|
.name = _name, \
|
|
}
|
|
|
|
struct subsys_cgs_check {
|
|
enum subsys_id id; /* the Subsys id */
|
|
struct pg_check_swcg *swcgs; /* those CGs that would be checked */
|
|
enum dbg_sys_id dbg_id; /*
|
|
* subsys_name is used in
|
|
* print_subsys_reg() and can be NULL
|
|
* if not porting ready yet.
|
|
*/
|
|
};
|
|
|
|
/*
|
|
* The clk names in Mediatek CCF.
|
|
*/
|
|
struct pg_check_swcg mm_swcgs[] = {
|
|
SWCG("mm_disp_mutex0"),
|
|
SWCG("mm_apb_bus"),
|
|
SWCG("mm_disp_ovl0"),
|
|
SWCG("mm_disp_rdma0"),
|
|
SWCG("mm_disp_ovl0_2l"),
|
|
SWCG("mm_disp_wdma0"),
|
|
SWCG("mm_disp_ccorr1"),
|
|
SWCG("mm_disp_rsz0"),
|
|
SWCG("mm_disp_aal0"),
|
|
SWCG("mm_disp_ccorr0"),
|
|
SWCG("mm_disp_color0"),
|
|
SWCG("mm_smi_infra"),
|
|
SWCG("mm_disp_dsc_wrap"),
|
|
SWCG("mm_disp_gamma0"),
|
|
SWCG("mm_disp_postmask0"),
|
|
SWCG("mm_disp_spr0"),
|
|
SWCG("mm_disp_dither0"),
|
|
SWCG("mm_smi_common"),
|
|
SWCG("mm_disp_cm0"),
|
|
SWCG("mm_dsi0"),
|
|
SWCG("mm_disp_fake_eng0"),
|
|
SWCG("mm_disp_fake_eng1"),
|
|
SWCG("mm_smi_gals"),
|
|
SWCG("mm_smi_iommu"),
|
|
SWCG(NULL),
|
|
};
|
|
|
|
struct pg_check_swcg mdp_swcgs[] = {
|
|
SWCG("mdp_rdma0"),
|
|
SWCG("mdp_tdshp0"),
|
|
SWCG("mdp_img_dl_async0"),
|
|
SWCG("mdp_img_dl_async1"),
|
|
SWCG("mdp_rdma1"),
|
|
SWCG("mdp_tdshp1"),
|
|
SWCG("mdp_smi0"),
|
|
SWCG("mdp_apb_bus"),
|
|
SWCG("mdp_wrot0"),
|
|
SWCG("mdp_rsz0"),
|
|
SWCG("mdp_hdr0"),
|
|
SWCG("mdp_mutex0"),
|
|
SWCG("mdp_wrot1"),
|
|
SWCG("mdp_rsz1"),
|
|
SWCG("mdp_fake_eng0"),
|
|
SWCG("mdp_aal0"),
|
|
SWCG("mdp_aal1"),
|
|
SWCG("mdp_color0"),
|
|
SWCG("mdp_img_dl_rel0_as0"),
|
|
SWCG("mdp_img_dl_rel1_as1"),
|
|
SWCG(NULL),
|
|
};
|
|
|
|
struct pg_check_swcg vdec_swcgs[] = {
|
|
SWCG("vdec_larb1_cken"),
|
|
SWCG("vdec_cken"),
|
|
SWCG("vdec_active"),
|
|
SWCG(NULL),
|
|
};
|
|
|
|
struct pg_check_swcg venc_swcgs[] = {
|
|
SWCG("venc_set0_larb"),
|
|
SWCG("venc_set1_venc"),
|
|
SWCG("jpgenc"),
|
|
SWCG("venc_set5_gals"),
|
|
SWCG(NULL),
|
|
};
|
|
|
|
struct pg_check_swcg img1_swcgs[] = {
|
|
SWCG("imgsys1_larb9"),
|
|
SWCG("imgsys1_larb10"),
|
|
SWCG("imgsys1_dip"),
|
|
SWCG("imgsys1_gals"),
|
|
SWCG(NULL),
|
|
};
|
|
|
|
struct pg_check_swcg img2_swcgs[] = {
|
|
SWCG("imgsys2_larb9"),
|
|
SWCG("imgsys2_larb10"),
|
|
SWCG("imgsys2_mfb"),
|
|
SWCG("imgsys2_wpe"),
|
|
SWCG("imgsys2_mss"),
|
|
SWCG("imgsys2_gals"),
|
|
SWCG(NULL),
|
|
};
|
|
|
|
struct pg_check_swcg ipe_swcgs[] = {
|
|
SWCG("ipe_larb19"),
|
|
SWCG("ipe_larb20"),
|
|
SWCG("ipe_smi_subcom"),
|
|
SWCG("ipe_fd"),
|
|
SWCG("ipe_fe"),
|
|
SWCG("ipe_rsc"),
|
|
SWCG("ipe_dpe"),
|
|
SWCG("ipe_gals"),
|
|
SWCG(NULL),
|
|
};
|
|
|
|
struct pg_check_swcg cam_swcgs[] = {
|
|
SWCG("cam_m_larb13"),
|
|
SWCG("cam_m_larb14"),
|
|
SWCG("cam_m_reserved0"),
|
|
SWCG("cam_m_cam"),
|
|
SWCG("cam_m_camtg"),
|
|
SWCG("cam_m_seninf"),
|
|
SWCG("cam_m_camsv1"),
|
|
SWCG("cam_m_camsv2"),
|
|
SWCG("cam_m_camsv3"),
|
|
SWCG("cam_m_ccu0"),
|
|
SWCG("cam_m_ccu1"),
|
|
SWCG("cam_m_mraw0"),
|
|
SWCG("cam_m_reserved2"),
|
|
SWCG("cam_m_fake_eng"),
|
|
SWCG("cam_m_ccu_gals"),
|
|
SWCG("cam_m_cam2mm_gals"),
|
|
SWCG(NULL),
|
|
};
|
|
|
|
struct pg_check_swcg cam_rawa_swcgs[] = {
|
|
SWCG("cam_ra_larbx"),
|
|
SWCG("cam_ra_cam"),
|
|
SWCG("cam_ra_camtg"),
|
|
SWCG(NULL),
|
|
};
|
|
|
|
struct pg_check_swcg cam_rawb_swcgs[] = {
|
|
SWCG("cam_rb_larbx"),
|
|
SWCG("cam_rb_cam"),
|
|
SWCG("cam_rb_camtg"),
|
|
SWCG(NULL),
|
|
};
|
|
|
|
struct subsys_cgs_check mtk_subsys_check[] = {
|
|
/*{SYS_DIS, mm_swcgs, NULL}, */
|
|
{SYS_DIS, mm_swcgs, mmsys},
|
|
{SYS_DIS, mdp_swcgs, mdpsys},
|
|
{SYS_VDE, vdec_swcgs, vdecsys},
|
|
{SYS_VEN, venc_swcgs, vencsys},
|
|
{SYS_ISP, img1_swcgs, img1sys},
|
|
{SYS_ISP2, img2_swcgs, img2sys},
|
|
{SYS_IPE, ipe_swcgs, ipesys},
|
|
{SYS_CAM, cam_swcgs, camsys},
|
|
{SYS_CAM_RAWA, cam_rawa_swcgs, cam_rawa_sys},
|
|
{SYS_CAM_RAWB, cam_rawb_swcgs, cam_rawb_sys},
|
|
};
|
|
|
|
static unsigned int check_cg_state(struct pg_check_swcg *swcg)
|
|
{
|
|
int enable_count = 0;
|
|
|
|
if (!swcg)
|
|
return 0;
|
|
|
|
while (swcg->name) {
|
|
if (!IS_ERR_OR_NULL(swcg->c)) {
|
|
if (__clk_get_enable_count(swcg->c) > 0) {
|
|
pr_notice("%s[%-17s: %3d]\n",
|
|
__func__,
|
|
__clk_get_name(swcg->c),
|
|
__clk_get_enable_count(swcg->c));
|
|
enable_count++;
|
|
}
|
|
}
|
|
swcg++;
|
|
}
|
|
|
|
return enable_count;
|
|
}
|
|
|
|
void mtk_check_subsys_swcg(enum subsys_id id)
|
|
{
|
|
int i;
|
|
unsigned int ret = 0;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mtk_subsys_check); i++) {
|
|
if (mtk_subsys_check[i].id != id)
|
|
continue;
|
|
|
|
/* check if Subsys CGs are still on */
|
|
ret = check_cg_state(mtk_subsys_check[i].swcgs);
|
|
if (ret) {
|
|
pr_notice("%s:(%d) warning!\n", __func__, id);
|
|
|
|
/* print registers dump */
|
|
print_subsys_reg(mtk_subsys_check[i].dbg_id);
|
|
}
|
|
}
|
|
|
|
if (ret) {
|
|
pr_notice("%s(%d): %d\n", __func__, id, ret);
|
|
BUG_ON(1);
|
|
}
|
|
}
|
|
|
|
static void __init pg_check_swcg_init_common(struct pg_check_swcg *swcg)
|
|
{
|
|
if (!swcg)
|
|
return;
|
|
|
|
while (swcg->name) {
|
|
struct clk *c = __clk_lookup(swcg->name);
|
|
|
|
if (IS_ERR_OR_NULL(c))
|
|
pr_notice("[%17s: NULL]\n", swcg->name);
|
|
else
|
|
swcg->c = c;
|
|
swcg++;
|
|
}
|
|
}
|
|
|
|
static int __init clkchk_init(void)
|
|
{
|
|
/* fill the 'struct clk *' ptr of every CGs*/
|
|
int i;
|
|
|
|
if (!of_machine_is_compatible("mediatek,MT6833"))
|
|
return -ENODEV;
|
|
|
|
register_syscore_ops(&clkchk_syscore_ops);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mtk_subsys_check); i++)
|
|
pg_check_swcg_init_common(mtk_subsys_check[i].swcgs);
|
|
|
|
return 0;
|
|
}
|
|
subsys_initcall(clkchk_init);
|