594 lines
15 KiB
C
Executable file
594 lines
15 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/list.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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#include <linux/uaccess.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/smp.h>
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/* #include <linux/earlysuspend.h> */
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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/* **** */
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/* #include <mach/mt_typedefs.h> */
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#include <mt-plat/sync_write.h>
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/*#include "mt_clkmgr.h"*/
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#include "mt6768_clkmgr.h"
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/* #include <mach/mt_dcm.h> */
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/* #include <mach/mt_idvfs.h> */ /* Fix when idvfs ready */
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/*#include "mt_spm.h"*/
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/*#include <mach/mt_spm_mtcmos.h>*/
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/* #include <mach/mt_spm_sleep.h> */
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/* #include <mach/mt_gpufreq.h> */
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/* #include <mach/irqs.h> */
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/* #include <mach/upmu_common.h> */
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/* #include <mach/upmu_sw.h> */
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/* #include <mach/upmu_hw.h> */
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/*#include "mt_freqhopping_drv.h"*/
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#ifdef CONFIG_OF
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#include <linux/of.h>
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#include <linux/of_address.h>
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#endif
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#ifdef CONFIG_OF
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void __iomem *clk_apmixed_base;
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void __iomem *clk_mcucfg_base;
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#endif
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#define PLL_ENABLE_WRITE 0
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/************************************************
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********** log debug **********
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************************************************/
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#define TAG "[Power/clkmgr] "
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#define clk_info(fmt, args...) \
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pr_info(TAG fmt, ##args)
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#define clk_dbg(fmt, args...) \
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pr_debug(TAG fmt, ##args)
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/************************************************
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********** register access **********
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************************************************/
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#define clk_readl(addr) \
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readl(addr)
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/* DRV_Reg32(addr) */
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#define clk_writel(addr, val) \
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mt_reg_sync_writel(val, addr)
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#define clk_setl(addr, val) \
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mt_reg_sync_writel(clk_readl(addr) | (val), addr)
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#define clk_clrl(addr, val) \
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mt_reg_sync_writel(clk_readl(addr) & ~(val), addr)
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/************************************************
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********** struct definition **********
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************************************************/
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/************************************************
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********** global variablies **********
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************************************************/
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/************************************************
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********** spin lock protect **********
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************************************************/
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/************************************************
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********** pll part **********
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************************************************/
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/************************************************
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********** subsys part **********
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************************************************/
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/*ARMPLL1*/
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#define ARMPLL_CON0 (clk_apmixed_base + 0x208)
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#define ARMPLL_CON1 (clk_apmixed_base + 0x20C)
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#define ARMPLL_CON2 (clk_apmixed_base + 0x210)
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#define ARMPLL_CON3 (clk_apmixed_base + 0x214)
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/*ARMPLL2*/
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#define ARMPLL_L_CON0 (clk_apmixed_base + 0x218)
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#define ARMPLL_L_CON1 (clk_apmixed_base + 0x21C)
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#define ARMPLL_L_CON2 (clk_apmixed_base + 0x220)
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#define ARMPLL_L_CON3 (clk_apmixed_base + 0x224)
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/*CCIPLL*/
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#define CCIPLL_CON0 (clk_apmixed_base + 0x228)
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#define CCIPLL_CON1 (clk_apmixed_base + 0x22C)
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#define CCIPLL_CON2 (clk_apmixed_base + 0x230)
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#define CCIPLL_CON3 (clk_apmixed_base + 0x234)
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/*GPUPLL*/
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#define MFGPLL_CON0 (clk_apmixed_base + 0x248)
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#define MFGPLL_CON1 (clk_apmixed_base + 0x24C)
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#define MFGPLL_CON2 (clk_apmixed_base + 0x250)
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#define MFGPLL_CON3 (clk_apmixed_base + 0x254)
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/*MMPLL*/
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#define MMPLL_CON0 (clk_apmixed_base + 0x31C)
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#define MMPLL_CON1 (clk_apmixed_base + 0x320)
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#define MMPLL_CON2 (clk_apmixed_base + 0x324)
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#define MMPLL_CON3 (clk_apmixed_base + 0x328)
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/* MCUCFG Register */
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#if 0
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#define MP0_PLL_DIV_CFG (clk_mcucfg_base + 0x7A0) /*ARMPLL_LL*/
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#define MP1_PLL_DIV_CFG (clk_mcucfg_base + 0x7A4) /*ARMPLL_L*/
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#define BUS_PLL_DIV_CFG (clk_mcucfg_base + 0x7C0) /*CCIPLL*/
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#endif
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/* MCUCFG Register */
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#define CPU_PLLDIV_CFG0 (clk_mcucfg_base + 0xA2A0) /* PLL_L, L-cores*/
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#define CPU_PLLDIV_CFG1 (clk_mcucfg_base + 0xA2A4) /* PLL, B-cores */
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#define BUS_PLLDIV_CFG (clk_mcucfg_base + 0xA2E0) /* CCIPLL */
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/************************************************
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********** cg_clk part **********
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************************************************/
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/************************************************
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********** initialization **********
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************************************************/
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/************************************************
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********** function debug **********
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************************************************/
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static int armpll1_fsel_read(struct seq_file *m, void *v)
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{
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return 0;
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}
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static int armpll2_fsel_read(struct seq_file *m, void *v)
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{
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return 0;
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}
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static int ccipll_fsel_read(struct seq_file *m, void *v)
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{
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return 0;
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}
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static int mmpll_fsel_read(struct seq_file *m, void *v)
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{
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return 0;
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}
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static int gpupll_fsel_read(struct seq_file *m, void *v)
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{
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return 0;
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}
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#if PLL_ENABLE_WRITE
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static void clk_dump(void)
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{
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clk_info("[ARMPLL_CON0]=0x%08x\n", clk_readl(ARMPLL_CON0));
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clk_info("[ARMPLL_CON1]=0x%08x\n", clk_readl(ARMPLL_CON1));
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clk_info("[ARMPLL_CON2]=0x%08x\n", clk_readl(ARMPLL_CON2));
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clk_info("[ARMPLL_CON3]=0x%08x\n", clk_readl(ARMPLL_CON3));
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clk_info("[CPU_PLLDIV_CFG1]=0x%08x\n", clk_readl(CPU_PLLDIV_CFG1));
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clk_info("[CCF] ARMPLL: %d\n", mt_get_abist_freq(22));
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clk_info("[ARMPLL_L_CON0]=0x%08x\n", clk_readl(ARMPLL_L_CON0));
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clk_info("[ARMPLL_L_CON1]=0x%08x\n", clk_readl(ARMPLL_L_CON1));
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clk_info("[ARMPLL_L_CON2]=0x%08x\n", clk_readl(ARMPLL_L_CON2));
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clk_info("[ARMPLL_L_CON3]=0x%08x\n", clk_readl(ARMPLL_L_CON3));
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clk_info("[CPU_PLLDIV_CFG0]=0x%08x\n", clk_readl(CPU_PLLDIV_CFG0));
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clk_info("[CCF] ARMPLL(L): %d\n", mt_get_abist_freq(21));
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clk_info("[CCIPLL_CON0]=0x%08x\n", clk_readl(CCIPLL_CON0));
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clk_info("[CCIPLL_CON1]=0x%08x\n", clk_readl(CCIPLL_CON1));
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clk_info("[CCIPLL_CON2]=0x%08x\n", clk_readl(CCIPLL_CON2));
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clk_info("[CCIPLL_CON3]=0x%08x\n", clk_readl(CCIPLL_CON3));
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clk_info("[BUS_PLLDIV_CFG]=0x%08x\n", clk_readl(BUS_PLLDIV_CFG));
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clk_info("[CCF] CCIPLL: %d\n", mt_get_abist_freq(49));
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}
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#define SDM_PLL_N_INFO_MASK 0x003FFFFF /*N_INFO[21:0]*/
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#define ARMPLL_POSDIV_MASK 0x07000000 /*POSDIV[26:24]*/
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#define SDM_PLL_N_INFO_CHG 0x80000000
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#define ARMPLL_DIV_MASK 0xFFE1FFFF /* DIVCK_SEL[21:17] */
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#define ARMPLL_DIV_SHIFT 17
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static int pll_div_value_map(int index)
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{
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int div = 0x08;
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switch (index) {
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case 1:
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div = 0x08;
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break;
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case 2:
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div = 0x0A;
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break;
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case 4:
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div = 0x0B;
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break;
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case 6:
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div = 0x1D;
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break;
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default:
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div = 0x08;
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break;
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}
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return div;
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}
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/*
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* ARMPLL(big cores) write operation.
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*/
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static ssize_t armpll1_fsel_write(struct file *file, const char __user *buffer,
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size_t count, loff_t *data)
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{
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char desc[32];
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int len = 0;
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unsigned int ctrl_value = 0;
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int div;
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unsigned int value = 0;
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len = (count < (sizeof(desc) - 1)) ? count : (sizeof(desc) - 1);
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if (copy_from_user(desc, buffer, len))
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return 0;
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desc[len] = '\0';
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if (sscanf(desc, "%x %x", &div, &value) == 2) {
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clk_dump();
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ctrl_value = clk_readl(ARMPLL_CON1);
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ctrl_value &= ~(SDM_PLL_N_INFO_MASK | ARMPLL_POSDIV_MASK);
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ctrl_value |= value &
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(SDM_PLL_N_INFO_MASK | ARMPLL_POSDIV_MASK);
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ctrl_value |= SDM_PLL_N_INFO_CHG;
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clk_writel(ARMPLL_CON1, ctrl_value);
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udelay(20);
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ctrl_value = clk_readl(CPU_PLLDIV_CFG1);
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ctrl_value &= ARMPLL_DIV_MASK;
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ctrl_value |= (pll_div_value_map(div) << ARMPLL_DIV_SHIFT);
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clk_writel(CPU_PLLDIV_CFG1, ctrl_value);
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}
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clk_dump();
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return count;
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}
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/*
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* ARMPLL_L(little cores) write operation.
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*/
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static ssize_t armpll2_fsel_write(struct file *file, const char __user *buffer,
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size_t count, loff_t *data)
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{
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char desc[32];
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int len = 0;
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unsigned int ctrl_value = 0;
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int div;
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unsigned int value;
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len = (count < (sizeof(desc) - 1)) ? count : (sizeof(desc) - 1);
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if (copy_from_user(desc, buffer, len))
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return 0;
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desc[len] = '\0';
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if (sscanf(desc, "%x %x", &div, &value) == 2) {
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clk_dump();
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ctrl_value = clk_readl(ARMPLL_L_CON1);
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ctrl_value &= ~(SDM_PLL_N_INFO_MASK | ARMPLL_POSDIV_MASK);
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ctrl_value |= value &
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(SDM_PLL_N_INFO_MASK | ARMPLL_POSDIV_MASK);
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ctrl_value |= SDM_PLL_N_INFO_CHG;
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clk_writel(ARMPLL_L_CON1, ctrl_value);
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udelay(20);
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ctrl_value = clk_readl(CPU_PLLDIV_CFG0);
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ctrl_value &= ARMPLL_DIV_MASK;
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ctrl_value |= (pll_div_value_map(div) << ARMPLL_DIV_SHIFT);
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clk_writel(CPU_PLLDIV_CFG0, ctrl_value);
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}
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clk_dump();
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return count;
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}
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static ssize_t ccipll_fsel_write(struct file *file, const char __user *buffer,
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size_t count, loff_t *data)
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{
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char desc[32];
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int len = 0;
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unsigned int ctrl_value = 0;
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int div;
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unsigned int value;
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len = (count < (sizeof(desc) - 1)) ? count : (sizeof(desc) - 1);
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if (copy_from_user(desc, buffer, len))
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return 0;
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desc[len] = '\0';
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if (sscanf(desc, "%x %x", &div, &value) == 2) {
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clk_dump();
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ctrl_value = clk_readl(CCIPLL_CON1);
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ctrl_value &= ~(SDM_PLL_N_INFO_MASK | ARMPLL_POSDIV_MASK);
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ctrl_value |= value &
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(SDM_PLL_N_INFO_MASK | ARMPLL_POSDIV_MASK);
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ctrl_value |= SDM_PLL_N_INFO_CHG;
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clk_writel(CCIPLL_CON1, ctrl_value);
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udelay(20);
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ctrl_value = clk_readl(BUS_PLLDIV_CFG);
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ctrl_value &= ARMPLL_DIV_MASK;
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ctrl_value |= (pll_div_value_map(div) << ARMPLL_DIV_SHIFT);
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clk_writel(BUS_PLLDIV_CFG, ctrl_value);
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}
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clk_dump();
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return count;
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}
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static ssize_t mmpll_fsel_write(struct file *file, const char __user *buffer,
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size_t count, loff_t *data)
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{
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char desc[32];
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int len = 0;
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unsigned int con0_value, con1_value;
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len = (count < (sizeof(desc) - 1)) ? count : (sizeof(desc) - 1);
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if (copy_from_user(desc, buffer, len))
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return 0;
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desc[len] = '\0';
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if (sscanf(desc, "%x %x", &con1_value, &con0_value) == 2) {
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clk_writel(MMPLL_CON1, con1_value);
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clk_writel(MMPLL_CON0, con0_value);
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udelay(20);
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}
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return count;
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}
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static ssize_t gpupll_fsel_write(struct file *file, const char __user *buffer,
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size_t count, loff_t *data)
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{
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char desc[32];
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int len = 0;
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unsigned int con0_value, con1_value;
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len = (count < (sizeof(desc) - 1)) ? count : (sizeof(desc) - 1);
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if (copy_from_user(desc, buffer, len))
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return 0;
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desc[len] = '\0';
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if (sscanf(desc, "%x %x", &con1_value, &con0_value) == 2) {
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clk_writel(MFGPLL_CON1, con1_value);
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clk_writel(MFGPLL_CON0, con0_value);
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udelay(20);
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}
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return count;
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}
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#endif /* PLL_ENABLE_WRITE */
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static int mm_clk_speed_dump_read(struct seq_file *m, void *v)
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{
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seq_printf(m, "%d\n", mt_get_abist_freq(27));
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return 0;
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}
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static int gpupll_speed_dump_read(struct seq_file *m, void *v)
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{
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seq_printf(m, "%d\n", mt_get_abist_freq(25));
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return 0;
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}
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static int univpll_speed_dump_read(struct seq_file *m, void *v)
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{
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seq_printf(m, "%d\n", mt_get_abist_freq(24));
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return 0;
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}
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/************ L ********************/
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static int proc_armpll1_fsel_open(struct inode *inode, struct file *file)
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{
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clk_info("%s", __func__);
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return single_open(file, armpll1_fsel_read, NULL);
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}
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static const struct file_operations armpll1_fsel_proc_fops = {
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.owner = THIS_MODULE,
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.open = proc_armpll1_fsel_open,
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.read = seq_read,
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#if PLL_ENABLE_WRITE
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.write = armpll1_fsel_write,
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#endif
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.release = single_release,
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};
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/************ LL ********************/
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static int proc_armpll2_fsel_open(struct inode *inode, struct file *file)
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{
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clk_info("%s", __func__);
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return single_open(file, armpll2_fsel_read, NULL);
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}
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static const struct file_operations armpll2_fsel_proc_fops = {
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.owner = THIS_MODULE,
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.open = proc_armpll2_fsel_open,
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.read = seq_read,
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#if PLL_ENABLE_WRITE
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.write = armpll2_fsel_write,
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#endif
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.release = single_release,
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};
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/************ CCI ********************/
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static int proc_ccipll_fsel_open(struct inode *inode, struct file *file)
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{
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clk_info("%s", __func__);
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return single_open(file, ccipll_fsel_read, NULL);
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}
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static const struct file_operations ccipll_fsel_proc_fops = {
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.owner = THIS_MODULE,
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.open = proc_ccipll_fsel_open,
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.read = seq_read,
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#if PLL_ENABLE_WRITE
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.write = ccipll_fsel_write,
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#endif
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.release = single_release,
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};
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/************ MM ********************/
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static int proc_mmpll_fsel_open(struct inode *inode, struct file *file)
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{
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clk_info("%s", __func__);
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return single_open(file, mmpll_fsel_read, NULL);
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}
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static const struct file_operations mmpll_fsel_proc_fops = {
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.owner = THIS_MODULE,
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.open = proc_mmpll_fsel_open,
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.read = seq_read,
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#if PLL_ENABLE_WRITE
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.write = mmpll_fsel_write,
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#endif
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.release = single_release,
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};
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/************ GPU ********************/
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static int proc_gpupll_fsel_open(struct inode *inode, struct file *file)
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{
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clk_info("%s", __func__);
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return single_open(file, gpupll_fsel_read, NULL);
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}
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static const struct file_operations gpupll_fsel_proc_fops = {
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.owner = THIS_MODULE,
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.open = proc_gpupll_fsel_open,
|
|
.read = seq_read,
|
|
#if PLL_ENABLE_WRITE
|
|
.write = gpupll_fsel_write,
|
|
#endif
|
|
.release = single_release,
|
|
};
|
|
/************ mm_clk ********************/
|
|
static int proc_mm_clk_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, mm_clk_speed_dump_read, NULL);
|
|
}
|
|
|
|
static const struct file_operations mm_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = proc_mm_clk_open,
|
|
.read = seq_read,
|
|
};
|
|
/************ gpupll ********************/
|
|
static int proc_gpupll_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, gpupll_speed_dump_read, NULL);
|
|
}
|
|
|
|
static const struct file_operations gpu_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = proc_gpupll_open,
|
|
.read = seq_read,
|
|
};
|
|
/************ univpll ********************/
|
|
static int proc_univpll_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, univpll_speed_dump_read, NULL);
|
|
}
|
|
|
|
static const struct file_operations univ_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = proc_univpll_open,
|
|
.read = seq_read,
|
|
};
|
|
|
|
void mt_clkmgr_debug_init(void)
|
|
{
|
|
/*use proc_create*/
|
|
struct proc_dir_entry *entry;
|
|
struct proc_dir_entry *clkmgr_dir;
|
|
|
|
clkmgr_dir = proc_mkdir("clkmgr", NULL);
|
|
if (!clkmgr_dir) {
|
|
pr_info("[%s]: fail to mkdir /proc/clkmgr\n", __func__);
|
|
return;
|
|
}
|
|
|
|
entry =
|
|
proc_create("armpll1_fsel", 0664, clkmgr_dir,
|
|
&armpll1_fsel_proc_fops);
|
|
entry =
|
|
proc_create("armpll2_fsel", 0664, clkmgr_dir,
|
|
&armpll2_fsel_proc_fops);
|
|
entry =
|
|
proc_create("ccipll_fsel", 0664, clkmgr_dir,
|
|
&ccipll_fsel_proc_fops);
|
|
entry =
|
|
proc_create("mmpll_fsel", 0664, clkmgr_dir,
|
|
&mmpll_fsel_proc_fops);
|
|
entry =
|
|
proc_create("gpupll_fsel", 0664, clkmgr_dir,
|
|
&gpupll_fsel_proc_fops);
|
|
entry =
|
|
proc_create("mm_speed_dump", 0444, clkmgr_dir,
|
|
&mm_fops);
|
|
entry =
|
|
proc_create("gpu_speed_dump", 0444, clkmgr_dir,
|
|
&gpu_fops);
|
|
entry =
|
|
proc_create("univpll_speed_dump", 0444, clkmgr_dir,
|
|
&univ_fops);
|
|
}
|
|
|
|
/*move to other place*/
|
|
int univpll_is_used(void)
|
|
{
|
|
/*
|
|
* 0: univpll is not used, sspm can disable
|
|
* 1: univpll is used, sspm cannot disable
|
|
*/
|
|
struct clk *c = __clk_lookup("univpll");
|
|
|
|
return __clk_get_enable_count(c);
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
void iomap(void)
|
|
{
|
|
struct device_node *node;
|
|
|
|
/*apmixed*/
|
|
node = of_find_compatible_node(NULL, NULL, "mediatek,apmixed");
|
|
if (!node)
|
|
pr_info("[CLK_APMIXED] find node failed\n");
|
|
clk_apmixed_base = of_iomap(node, 0);
|
|
if (!clk_apmixed_base)
|
|
pr_info("[CLK_APMIXED] base failed\n");
|
|
|
|
/*mcucfg*/
|
|
node = of_find_compatible_node(NULL, NULL, "mediatek,mcucfg");
|
|
if (!node)
|
|
pr_info("[CLK_MCUCFG] find node failed\n");
|
|
clk_mcucfg_base = of_iomap(node, 0);
|
|
if (!clk_mcucfg_base)
|
|
pr_info("[CLK_MCUCFG] base failed\n");
|
|
}
|
|
#endif
|
|
|
|
|
|
static int mt_clkmgr_debug_module_init(void)
|
|
{
|
|
iomap();
|
|
mt_clkmgr_debug_init();
|
|
return 0;
|
|
}
|
|
|
|
module_init(mt_clkmgr_debug_module_init);
|