558 lines
16 KiB
C
Executable file
558 lines
16 KiB
C
Executable file
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "pp_debug.h"
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <drm/amdgpu_drm.h>
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#include "power_state.h"
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#include "hwmgr.h"
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#include "ppsmc.h"
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#include "amd_acpi.h"
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#include "pp_psm.h"
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extern const struct pp_smumgr_func ci_smu_funcs;
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extern const struct pp_smumgr_func smu8_smu_funcs;
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extern const struct pp_smumgr_func iceland_smu_funcs;
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extern const struct pp_smumgr_func tonga_smu_funcs;
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extern const struct pp_smumgr_func fiji_smu_funcs;
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extern const struct pp_smumgr_func polaris10_smu_funcs;
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extern const struct pp_smumgr_func vegam_smu_funcs;
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extern const struct pp_smumgr_func vega10_smu_funcs;
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extern const struct pp_smumgr_func vega12_smu_funcs;
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extern const struct pp_smumgr_func smu10_smu_funcs;
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extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
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extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
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extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
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extern int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
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extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
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static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
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static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
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static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
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static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
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static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
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static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
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static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
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static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
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{
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hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 2;
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hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 0;
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hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 1;
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hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 3;
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hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 4;
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hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_POWERSAVING;
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hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_VIDEO;
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hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
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hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VR;
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hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE;
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}
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int hwmgr_early_init(struct pp_hwmgr *hwmgr)
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{
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if (!hwmgr)
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return -EINVAL;
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hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
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hwmgr->pp_table_version = PP_TABLE_V1;
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hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
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hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
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hwmgr_init_default_caps(hwmgr);
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hwmgr_set_user_specify_caps(hwmgr);
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hwmgr->fan_ctrl_is_in_default_mode = true;
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hwmgr->reload_fw = 1;
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hwmgr_init_workload_prority(hwmgr);
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switch (hwmgr->chip_family) {
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case AMDGPU_FAMILY_CI:
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hwmgr->smumgr_funcs = &ci_smu_funcs;
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ci_set_asic_special_caps(hwmgr);
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hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
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PP_ENABLE_GFX_CG_THRU_SMU |
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PP_GFXOFF_MASK);
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hwmgr->pp_table_version = PP_TABLE_V0;
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hwmgr->od_enabled = false;
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smu7_init_function_pointers(hwmgr);
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break;
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case AMDGPU_FAMILY_CZ:
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hwmgr->od_enabled = false;
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hwmgr->smumgr_funcs = &smu8_smu_funcs;
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hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
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smu8_init_function_pointers(hwmgr);
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break;
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case AMDGPU_FAMILY_VI:
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hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
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switch (hwmgr->chip_id) {
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case CHIP_TOPAZ:
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hwmgr->smumgr_funcs = &iceland_smu_funcs;
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topaz_set_asic_special_caps(hwmgr);
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hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
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PP_ENABLE_GFX_CG_THRU_SMU);
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hwmgr->pp_table_version = PP_TABLE_V0;
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hwmgr->od_enabled = false;
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break;
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case CHIP_TONGA:
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hwmgr->smumgr_funcs = &tonga_smu_funcs;
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tonga_set_asic_special_caps(hwmgr);
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hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
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break;
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case CHIP_FIJI:
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hwmgr->smumgr_funcs = &fiji_smu_funcs;
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fiji_set_asic_special_caps(hwmgr);
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hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
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PP_ENABLE_GFX_CG_THRU_SMU);
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break;
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case CHIP_POLARIS11:
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case CHIP_POLARIS10:
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case CHIP_POLARIS12:
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hwmgr->smumgr_funcs = &polaris10_smu_funcs;
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polaris_set_asic_special_caps(hwmgr);
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hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
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break;
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case CHIP_VEGAM:
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hwmgr->smumgr_funcs = &vegam_smu_funcs;
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polaris_set_asic_special_caps(hwmgr);
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hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
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break;
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default:
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return -EINVAL;
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}
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smu7_init_function_pointers(hwmgr);
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break;
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case AMDGPU_FAMILY_AI:
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switch (hwmgr->chip_id) {
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case CHIP_VEGA10:
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case CHIP_VEGA20:
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hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
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hwmgr->smumgr_funcs = &vega10_smu_funcs;
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vega10_hwmgr_init(hwmgr);
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break;
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case CHIP_VEGA12:
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hwmgr->smumgr_funcs = &vega12_smu_funcs;
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vega12_hwmgr_init(hwmgr);
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break;
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default:
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return -EINVAL;
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}
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break;
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case AMDGPU_FAMILY_RV:
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switch (hwmgr->chip_id) {
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case CHIP_RAVEN:
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hwmgr->od_enabled = false;
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hwmgr->smumgr_funcs = &smu10_smu_funcs;
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smu10_init_function_pointers(hwmgr);
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break;
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default:
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return -EINVAL;
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}
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
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{
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if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
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return -EINVAL;
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phm_register_irq_handlers(hwmgr);
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return hwmgr->smumgr_funcs->smu_init(hwmgr);
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}
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int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
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{
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if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
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hwmgr->smumgr_funcs->smu_fini(hwmgr);
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return 0;
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}
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int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
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{
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int ret = 0;
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if (!hwmgr || !hwmgr->smumgr_funcs)
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return -EINVAL;
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if (hwmgr->smumgr_funcs->start_smu) {
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ret = hwmgr->smumgr_funcs->start_smu(hwmgr);
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if (ret) {
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pr_err("smc start failed\n");
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return -EINVAL;
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}
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}
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if (!hwmgr->pm_en)
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return 0;
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if (!hwmgr->pptable_func ||
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!hwmgr->pptable_func->pptable_init ||
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!hwmgr->hwmgr_func->backend_init) {
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hwmgr->pm_en = false;
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pr_info("dpm not supported \n");
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return 0;
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}
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ret = hwmgr->pptable_func->pptable_init(hwmgr);
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if (ret)
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goto err;
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((struct amdgpu_device *)hwmgr->adev)->pm.no_fan =
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hwmgr->thermal_controller.fanInfo.bNoFan;
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ret = hwmgr->hwmgr_func->backend_init(hwmgr);
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if (ret)
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goto err1;
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/* make sure dc limits are valid */
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if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
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(hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0))
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hwmgr->dyn_state.max_clock_voltage_on_dc =
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hwmgr->dyn_state.max_clock_voltage_on_ac;
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ret = psm_init_power_state_table(hwmgr);
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if (ret)
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goto err2;
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ret = phm_setup_asic(hwmgr);
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if (ret)
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goto err2;
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ret = phm_enable_dynamic_state_management(hwmgr);
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if (ret)
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goto err2;
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ret = phm_start_thermal_controller(hwmgr);
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ret |= psm_set_performance_states(hwmgr);
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if (ret)
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goto err2;
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((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true;
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return 0;
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err2:
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if (hwmgr->hwmgr_func->backend_fini)
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hwmgr->hwmgr_func->backend_fini(hwmgr);
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err1:
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if (hwmgr->pptable_func->pptable_fini)
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hwmgr->pptable_func->pptable_fini(hwmgr);
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err:
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return ret;
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}
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int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
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{
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if (!hwmgr || !hwmgr->pm_en)
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return 0;
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phm_stop_thermal_controller(hwmgr);
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psm_set_boot_states(hwmgr);
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psm_adjust_power_state_dynamic(hwmgr, false, NULL);
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phm_disable_dynamic_state_management(hwmgr);
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phm_disable_clock_power_gatings(hwmgr);
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if (hwmgr->hwmgr_func->backend_fini)
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hwmgr->hwmgr_func->backend_fini(hwmgr);
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if (hwmgr->pptable_func->pptable_fini)
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hwmgr->pptable_func->pptable_fini(hwmgr);
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return psm_fini_power_state_table(hwmgr);
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}
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int hwmgr_suspend(struct pp_hwmgr *hwmgr)
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{
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int ret = 0;
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if (!hwmgr || !hwmgr->pm_en)
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return 0;
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phm_disable_smc_firmware_ctf(hwmgr);
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ret = psm_set_boot_states(hwmgr);
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if (ret)
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return ret;
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ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
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if (ret)
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return ret;
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ret = phm_power_down_asic(hwmgr);
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return ret;
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}
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int hwmgr_resume(struct pp_hwmgr *hwmgr)
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{
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int ret = 0;
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if (!hwmgr)
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return -EINVAL;
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if (hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->start_smu) {
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if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
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pr_err("smc start failed\n");
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return -EINVAL;
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}
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}
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if (!hwmgr->pm_en)
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return 0;
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ret = phm_setup_asic(hwmgr);
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if (ret)
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return ret;
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ret = phm_enable_dynamic_state_management(hwmgr);
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if (ret)
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return ret;
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ret = phm_start_thermal_controller(hwmgr);
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ret |= psm_set_performance_states(hwmgr);
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if (ret)
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return ret;
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ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
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return ret;
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}
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static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state)
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{
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switch (state) {
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case POWER_STATE_TYPE_BATTERY:
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return PP_StateUILabel_Battery;
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case POWER_STATE_TYPE_BALANCED:
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return PP_StateUILabel_Balanced;
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case POWER_STATE_TYPE_PERFORMANCE:
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return PP_StateUILabel_Performance;
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default:
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return PP_StateUILabel_None;
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}
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}
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int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
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enum amd_pm_state_type *user_state)
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{
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int ret = 0;
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if (hwmgr == NULL)
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return -EINVAL;
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switch (task_id) {
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case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
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ret = phm_pre_display_configuration_changed(hwmgr);
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if (ret)
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return ret;
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ret = phm_set_cpu_power_state(hwmgr);
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if (ret)
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return ret;
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ret = psm_set_performance_states(hwmgr);
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if (ret)
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return ret;
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ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
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break;
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case AMD_PP_TASK_ENABLE_USER_STATE:
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{
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enum PP_StateUILabel requested_ui_label;
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struct pp_power_state *requested_ps = NULL;
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if (user_state == NULL) {
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ret = -EINVAL;
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break;
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}
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requested_ui_label = power_state_convert(*user_state);
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ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
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if (ret)
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return ret;
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ret = psm_adjust_power_state_dynamic(hwmgr, false, requested_ps);
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break;
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}
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case AMD_PP_TASK_COMPLETE_INIT:
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case AMD_PP_TASK_READJUST_POWER_STATE:
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ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
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break;
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default:
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break;
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}
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return ret;
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}
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void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
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{
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
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phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
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phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
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#if defined(CONFIG_ACPI)
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if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))
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phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
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#endif
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_DynamicPatchPowerState);
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_EnableSMU7ThermalManagement);
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_DynamicPowerManagement);
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_SMC);
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_DynamicUVDState);
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_FanSpeedInTableIsRPM);
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return;
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}
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int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
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{
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if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_SclkDeepSleep);
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else
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_SclkDeepSleep);
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if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_PowerContainment);
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_CAC);
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} else {
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_PowerContainment);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_CAC);
|
|
}
|
|
|
|
if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
|
|
hwmgr->od_enabled = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
|
|
{
|
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_EVV);
|
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_SQRamping);
|
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_RegulatorHot);
|
|
|
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_AutomaticDCTransition);
|
|
|
|
if (hwmgr->chip_id != CHIP_POLARIS10)
|
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_SPLLShutdownSupport);
|
|
|
|
if (hwmgr->chip_id != CHIP_POLARIS11) {
|
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_DBRamping);
|
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_TDRamping);
|
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_TCPRamping);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
|
|
{
|
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_EVV);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_SQRamping);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_DBRamping);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_TDRamping);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_TCPRamping);
|
|
return 0;
|
|
}
|
|
|
|
int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
|
|
{
|
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_EVV);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_SQRamping);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_DBRamping);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_TDRamping);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_TCPRamping);
|
|
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_UVDPowerGating);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_VCEPowerGating);
|
|
return 0;
|
|
}
|
|
|
|
int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
|
|
{
|
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_EVV);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_SQRamping);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_DBRamping);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_TDRamping);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_TCPRamping);
|
|
return 0;
|
|
}
|
|
|
|
int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
|
|
{
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_SQRamping);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_DBRamping);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_TDRamping);
|
|
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_TCPRamping);
|
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_MemorySpreadSpectrumSupport);
|
|
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
|
PHM_PlatformCaps_EngineSpreadSpectrumSupport);
|
|
return 0;
|
|
}
|