712 lines
22 KiB
C
Executable file
712 lines
22 KiB
C
Executable file
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef _INTEL_GUC_FWIF_H
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#define _INTEL_GUC_FWIF_H
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#define GUC_CLIENT_PRIORITY_KMD_HIGH 0
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#define GUC_CLIENT_PRIORITY_HIGH 1
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#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
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#define GUC_CLIENT_PRIORITY_NORMAL 3
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#define GUC_CLIENT_PRIORITY_NUM 4
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#define GUC_MAX_STAGE_DESCRIPTORS 1024
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#define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS
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#define GUC_RENDER_ENGINE 0
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#define GUC_VIDEO_ENGINE 1
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#define GUC_BLITTER_ENGINE 2
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#define GUC_VIDEOENHANCE_ENGINE 3
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#define GUC_VIDEO_ENGINE2 4
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#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
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/* Work queue item header definitions */
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#define WQ_STATUS_ACTIVE 1
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#define WQ_STATUS_SUSPENDED 2
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#define WQ_STATUS_CMD_ERROR 3
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#define WQ_STATUS_ENGINE_ID_NOT_USED 4
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#define WQ_STATUS_SUSPENDED_FROM_RESET 5
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#define WQ_TYPE_SHIFT 0
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#define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT)
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#define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT)
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#define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT)
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#define WQ_TARGET_SHIFT 10
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#define WQ_LEN_SHIFT 16
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#define WQ_NO_WCFLUSH_WAIT (1 << 27)
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#define WQ_PRESENT_WORKLOAD (1 << 28)
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#define WQ_RING_TAIL_SHIFT 20
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#define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */
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#define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT)
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#define GUC_DOORBELL_ENABLED 1
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#define GUC_DOORBELL_DISABLED 0
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#define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)
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#define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)
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#define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)
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#define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)
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#define GUC_STAGE_DESC_ATTR_RESET BIT(4)
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#define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)
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#define GUC_STAGE_DESC_ATTR_PCH BIT(6)
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#define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
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/* The guc control data is 10 DWORDs */
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#define GUC_CTL_CTXINFO 0
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#define GUC_CTL_CTXNUM_IN16_SHIFT 0
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#define GUC_CTL_BASE_ADDR_SHIFT 12
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#define GUC_CTL_ARAT_HIGH 1
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#define GUC_CTL_ARAT_LOW 2
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#define GUC_CTL_DEVICE_INFO 3
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#define GUC_CTL_LOG_PARAMS 4
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#define GUC_LOG_VALID (1 << 0)
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#define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
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#define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3)
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#define GUC_LOG_CRASH_SHIFT 4
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#define GUC_LOG_CRASH_MASK (0x1 << GUC_LOG_CRASH_SHIFT)
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#define GUC_LOG_DPC_SHIFT 6
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#define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT)
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#define GUC_LOG_ISR_SHIFT 9
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#define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT)
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#define GUC_LOG_BUF_ADDR_SHIFT 12
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#define GUC_CTL_PAGE_FAULT_CONTROL 5
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#define GUC_CTL_WA 6
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#define GUC_CTL_WA_UK_BY_DRIVER (1 << 3)
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#define GUC_CTL_FEATURE 7
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#define GUC_CTL_VCS2_ENABLED (1 << 0)
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#define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1)
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#define GUC_CTL_FEATURE2 (1 << 2)
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#define GUC_CTL_POWER_GATING (1 << 3)
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#define GUC_CTL_DISABLE_SCHEDULER (1 << 4)
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#define GUC_CTL_PREEMPTION_LOG (1 << 5)
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#define GUC_CTL_ENABLE_SLPC (1 << 7)
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#define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8)
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#define GUC_CTL_DEBUG 8
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#define GUC_LOG_VERBOSITY_SHIFT 0
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#define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
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/* Verbosity range-check limits, without the shift */
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#define GUC_LOG_VERBOSITY_MIN 0
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#define GUC_LOG_VERBOSITY_MAX 3
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#define GUC_LOG_VERBOSITY_MASK 0x0000000f
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#define GUC_LOG_DESTINATION_MASK (3 << 4)
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#define GUC_LOG_DISABLED (1 << 6)
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#define GUC_PROFILE_ENABLED (1 << 7)
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#define GUC_WQ_TRACK_ENABLED (1 << 8)
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#define GUC_ADS_ENABLED (1 << 9)
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#define GUC_LOG_DEFAULT_DISABLED (1 << 10)
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#define GUC_ADS_ADDR_SHIFT 11
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#define GUC_ADS_ADDR_MASK 0xfffff800
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#define GUC_CTL_RSRVD 9
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#define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
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/**
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* DOC: GuC Firmware Layout
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*
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* The GuC firmware layout looks like this:
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*
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* +-------------------------------+
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* | uc_css_header |
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* | |
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* | contains major/minor version |
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* +-------------------------------+
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* | uCode |
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* +-------------------------------+
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* | RSA signature |
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* +-------------------------------+
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* | modulus key |
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* +-------------------------------+
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* | exponent val |
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* +-------------------------------+
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*
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* The firmware may or may not have modulus key and exponent data. The header,
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* uCode and RSA signature are must-have components that will be used by driver.
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* Length of each components, which is all in dwords, can be found in header.
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* In the case that modulus and exponent are not present in fw, a.k.a truncated
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* image, the length value still appears in header.
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*
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* Driver will do some basic fw size validation based on the following rules:
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*
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* 1. Header, uCode and RSA are must-have components.
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* 2. All firmware components, if they present, are in the sequence illustrated
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* in the layout table above.
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* 3. Length info of each component can be found in header, in dwords.
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* 4. Modulus and exponent key are not required by driver. They may not appear
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* in fw. So driver will load a truncated firmware in this case.
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*
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* HuC firmware layout is same as GuC firmware.
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*
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* HuC firmware css header is different. However, the only difference is where
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* the version information is saved. The uc_css_header is unified to support
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* both. Driver should get HuC version from uc_css_header.huc_sw_version, while
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* uc_css_header.guc_sw_version for GuC.
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*/
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struct uc_css_header {
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u32 module_type;
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/* header_size includes all non-uCode bits, including css_header, rsa
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* key, modulus key and exponent data. */
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u32 header_size_dw;
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u32 header_version;
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u32 module_id;
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u32 module_vendor;
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union {
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struct {
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u8 day;
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u8 month;
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u16 year;
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};
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u32 date;
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};
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u32 size_dw; /* uCode plus header_size_dw */
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u32 key_size_dw;
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u32 modulus_size_dw;
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u32 exponent_size_dw;
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union {
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struct {
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u8 hour;
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u8 min;
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u16 sec;
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};
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u32 time;
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};
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char username[8];
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char buildnumber[12];
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union {
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struct {
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u32 branch_client_version;
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u32 sw_version;
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} guc;
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struct {
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u32 sw_version;
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u32 reserved;
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} huc;
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};
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u32 prod_preprod_fw;
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u32 reserved[12];
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u32 header_info;
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} __packed;
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struct guc_doorbell_info {
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u32 db_status;
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u32 cookie;
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u32 reserved[14];
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} __packed;
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union guc_doorbell_qw {
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struct {
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u32 db_status;
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u32 cookie;
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};
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u64 value_qw;
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} __packed;
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#define GUC_NUM_DOORBELLS 256
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#define GUC_DOORBELL_INVALID (GUC_NUM_DOORBELLS)
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#define GUC_DB_SIZE (PAGE_SIZE)
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#define GUC_WQ_SIZE (PAGE_SIZE * 2)
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/* Work item for submitting workloads into work queue of GuC. */
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struct guc_wq_item {
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u32 header;
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u32 context_desc;
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u32 submit_element_info;
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u32 fence_id;
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} __packed;
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struct guc_process_desc {
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u32 stage_id;
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u64 db_base_addr;
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u32 head;
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u32 tail;
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u32 error_offset;
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u64 wq_base_addr;
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u32 wq_size_bytes;
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u32 wq_status;
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u32 engine_presence;
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u32 priority;
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u32 reserved[30];
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} __packed;
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/* engine id and context id is packed into guc_execlist_context.context_id*/
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#define GUC_ELC_CTXID_OFFSET 0
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#define GUC_ELC_ENGINE_OFFSET 29
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/* The execlist context including software and HW information */
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struct guc_execlist_context {
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u32 context_desc;
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u32 context_id;
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u32 ring_status;
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u32 ring_lrca;
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u32 ring_begin;
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u32 ring_end;
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u32 ring_next_free_location;
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u32 ring_current_tail_pointer_value;
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u8 engine_state_submit_value;
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u8 engine_state_wait_value;
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u16 pagefault_count;
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u16 engine_submit_queue_count;
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} __packed;
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/*
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* This structure describes a stage set arranged for a particular communication
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* between uKernel (GuC) and Driver (KMD). Technically, this is known as a
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* "GuC Context descriptor" in the specs, but we use the term "stage descriptor"
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* to avoid confusion with all the other things already named "context" in the
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* driver. A static pool of these descriptors are stored inside a GEM object
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* (stage_desc_pool) which is held for the entire lifetime of our interaction
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* with the GuC, being allocated before the GuC is loaded with its firmware.
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*/
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struct guc_stage_desc {
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u32 sched_common_area;
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u32 stage_id;
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u32 pas_id;
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u8 engines_used;
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u64 db_trigger_cpu;
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u32 db_trigger_uk;
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u64 db_trigger_phy;
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u16 db_id;
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struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM];
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u8 attribute;
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u32 priority;
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u32 wq_sampled_tail_offset;
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u32 wq_total_submit_enqueues;
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u32 process_desc;
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u32 wq_addr;
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u32 wq_size;
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u32 engine_presence;
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u8 engine_suspended;
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u8 reserved0[3];
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u64 reserved1[1];
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u64 desc_private;
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} __packed;
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/**
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* DOC: CTB based communication
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*
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* The CTB (command transport buffer) communication between Host and GuC
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* is based on u32 data stream written to the shared buffer. One buffer can
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* be used to transmit data only in one direction (one-directional channel).
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*
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* Current status of the each buffer is stored in the buffer descriptor.
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* Buffer descriptor holds tail and head fields that represents active data
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* stream. The tail field is updated by the data producer (sender), and head
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* field is updated by the data consumer (receiver)::
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*
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* +------------+
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* | DESCRIPTOR | +=================+============+========+
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* +============+ | | MESSAGE(s) | |
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* | address |--------->+=================+============+========+
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* +------------+
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* | head | ^-----head--------^
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* +------------+
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* | tail | ^---------tail-----------------^
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* +------------+
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* | size | ^---------------size--------------------^
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* +------------+
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*
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* Each message in data stream starts with the single u32 treated as a header,
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* followed by optional set of u32 data that makes message specific payload::
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*
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* +------------+---------+---------+---------+
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* | MESSAGE |
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* +------------+---------+---------+---------+
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* | msg[0] | [1] | ... | [n-1] |
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* +------------+---------+---------+---------+
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* | MESSAGE | MESSAGE PAYLOAD |
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* + HEADER +---------+---------+---------+
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* | | 0 | ... | n |
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* +======+=====+=========+=========+=========+
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* | 31:16| code| | | |
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* +------+-----+ | | |
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* | 15:5|flags| | | |
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* +------+-----+ | | |
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* | 4:0| len| | | |
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* +------+-----+---------+---------+---------+
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*
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* ^-------------len-------------^
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*
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* The message header consists of:
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*
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* - **len**, indicates length of the message payload (in u32)
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* - **code**, indicates message code
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* - **flags**, holds various bits to control message handling
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*/
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/*
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* Describes single command transport buffer.
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* Used by both guc-master and clients.
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*/
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struct guc_ct_buffer_desc {
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u32 addr; /* gfx address */
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u64 host_private; /* host private data */
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u32 size; /* size in bytes */
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u32 head; /* offset updated by GuC*/
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u32 tail; /* offset updated by owner */
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u32 is_in_error; /* error indicator */
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u32 fence; /* fence updated by GuC */
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u32 status; /* status updated by GuC */
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u32 owner; /* id of the channel owner */
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u32 owner_sub_id; /* owner-defined field for extra tracking */
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u32 reserved[5];
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} __packed;
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/* Type of command transport buffer */
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#define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u
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#define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u
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/*
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* Definition of the command transport message header (DW0)
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*
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* bit[4..0] message len (in dwords)
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* bit[7..5] reserved
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* bit[8] write fence to desc
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* bit[9] write status to H2G buff
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* bit[10] send status (via G2H)
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* bit[15..11] reserved
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* bit[31..16] action code
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*/
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#define GUC_CT_MSG_LEN_SHIFT 0
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#define GUC_CT_MSG_LEN_MASK 0x1F
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#define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8)
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#define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9)
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#define GUC_CT_MSG_SEND_STATUS (1 << 10)
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#define GUC_CT_MSG_ACTION_SHIFT 16
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#define GUC_CT_MSG_ACTION_MASK 0xFFFF
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#define GUC_FORCEWAKE_RENDER (1 << 0)
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#define GUC_FORCEWAKE_MEDIA (1 << 1)
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#define GUC_POWER_UNSPECIFIED 0
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#define GUC_POWER_D0 1
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#define GUC_POWER_D1 2
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#define GUC_POWER_D2 3
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#define GUC_POWER_D3 4
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/* Scheduling policy settings */
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/* Reset engine upon preempt failure */
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#define POLICY_RESET_ENGINE (1<<0)
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/* Preempt to idle on quantum expiry */
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#define POLICY_PREEMPT_TO_IDLE (1<<1)
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#define POLICY_MAX_NUM_WI 15
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#define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
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#define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
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#define POLICY_DEFAULT_PREEMPTION_TIME_US 500000
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#define POLICY_DEFAULT_FAULT_TIME_US 250000
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struct guc_policy {
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/* Time for one workload to execute. (in micro seconds) */
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u32 execution_quantum;
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u32 reserved1;
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/* Time to wait for a preemption request to completed before issuing a
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* reset. (in micro seconds). */
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u32 preemption_time;
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/* How much time to allow to run after the first fault is observed.
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* Then preempt afterwards. (in micro seconds) */
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u32 fault_time;
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u32 policy_flags;
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u32 reserved[2];
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} __packed;
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struct guc_policies {
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struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINES_NUM];
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/* In micro seconds. How much time to allow before DPC processing is
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* called back via interrupt (to prevent DPC queue drain starving).
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* Typically 1000s of micro seconds (example only, not granularity). */
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u32 dpc_promote_time;
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/* Must be set to take these new values. */
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u32 is_valid;
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/* Max number of WIs to process per call. A large value may keep CS
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* idle. */
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u32 max_num_work_items;
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u32 reserved[19];
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} __packed;
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/* GuC MMIO reg state struct */
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#define GUC_REGSET_FLAGS_NONE 0x0
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#define GUC_REGSET_POWERCYCLE 0x1
|
|
#define GUC_REGSET_MASKED 0x2
|
|
#define GUC_REGSET_ENGINERESET 0x4
|
|
#define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8
|
|
#define GUC_REGSET_SAVE_CURRENT_VALUE 0x10
|
|
|
|
#define GUC_REGSET_MAX_REGISTERS 25
|
|
#define GUC_MMIO_WHITE_LIST_START 0x24d0
|
|
#define GUC_MMIO_WHITE_LIST_MAX 12
|
|
#define GUC_S3_SAVE_SPACE_PAGES 10
|
|
|
|
struct guc_mmio_regset {
|
|
struct __packed {
|
|
u32 offset;
|
|
u32 value;
|
|
u32 flags;
|
|
} registers[GUC_REGSET_MAX_REGISTERS];
|
|
|
|
u32 values_valid;
|
|
u32 number_of_registers;
|
|
} __packed;
|
|
|
|
/* MMIO registers that are set as non privileged */
|
|
struct mmio_white_list {
|
|
u32 mmio_start;
|
|
u32 offsets[GUC_MMIO_WHITE_LIST_MAX];
|
|
u32 count;
|
|
} __packed;
|
|
|
|
struct guc_mmio_reg_state {
|
|
struct guc_mmio_regset global_reg;
|
|
struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM];
|
|
struct mmio_white_list white_list[GUC_MAX_ENGINES_NUM];
|
|
} __packed;
|
|
|
|
/* GuC Additional Data Struct */
|
|
|
|
struct guc_ads {
|
|
u32 reg_state_addr;
|
|
u32 reg_state_buffer;
|
|
u32 golden_context_lrca;
|
|
u32 scheduler_policies;
|
|
u32 reserved0[3];
|
|
u32 eng_state_size[GUC_MAX_ENGINES_NUM];
|
|
u32 reserved2[4];
|
|
} __packed;
|
|
|
|
/* GuC logging structures */
|
|
|
|
enum guc_log_buffer_type {
|
|
GUC_ISR_LOG_BUFFER,
|
|
GUC_DPC_LOG_BUFFER,
|
|
GUC_CRASH_DUMP_LOG_BUFFER,
|
|
GUC_MAX_LOG_BUFFER
|
|
};
|
|
|
|
/**
|
|
* Below state structure is used for coordination of retrieval of GuC firmware
|
|
* logs. Separate state is maintained for each log buffer type.
|
|
* read_ptr points to the location where i915 read last in log buffer and
|
|
* is read only for GuC firmware. write_ptr is incremented by GuC with number
|
|
* of bytes written for each log entry and is read only for i915.
|
|
* When any type of log buffer becomes half full, GuC sends a flush interrupt.
|
|
* GuC firmware expects that while it is writing to 2nd half of the buffer,
|
|
* first half would get consumed by Host and then get a flush completed
|
|
* acknowledgment from Host, so that it does not end up doing any overwrite
|
|
* causing loss of logs. So when buffer gets half filled & i915 has requested
|
|
* for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr
|
|
* to the value of write_ptr and raise the interrupt.
|
|
* On receiving the interrupt i915 should read the buffer, clear flush_to_file
|
|
* field and also update read_ptr with the value of sample_write_ptr, before
|
|
* sending an acknowledgment to GuC. marker & version fields are for internal
|
|
* usage of GuC and opaque to i915. buffer_full_cnt field is incremented every
|
|
* time GuC detects the log buffer overflow.
|
|
*/
|
|
struct guc_log_buffer_state {
|
|
u32 marker[2];
|
|
u32 read_ptr;
|
|
u32 write_ptr;
|
|
u32 size;
|
|
u32 sampled_write_ptr;
|
|
union {
|
|
struct {
|
|
u32 flush_to_file:1;
|
|
u32 buffer_full_cnt:4;
|
|
u32 reserved:27;
|
|
};
|
|
u32 flags;
|
|
};
|
|
u32 version;
|
|
} __packed;
|
|
|
|
struct guc_ctx_report {
|
|
u32 report_return_status;
|
|
u32 reserved1[64];
|
|
u32 affected_count;
|
|
u32 reserved2[2];
|
|
} __packed;
|
|
|
|
/* GuC Shared Context Data Struct */
|
|
struct guc_shared_ctx_data {
|
|
u32 addr_of_last_preempted_data_low;
|
|
u32 addr_of_last_preempted_data_high;
|
|
u32 addr_of_last_preempted_data_high_tmp;
|
|
u32 padding;
|
|
u32 is_mapped_to_proxy;
|
|
u32 proxy_ctx_id;
|
|
u32 engine_reset_ctx_id;
|
|
u32 media_reset_count;
|
|
u32 reserved1[8];
|
|
u32 uk_last_ctx_switch_reason;
|
|
u32 was_reset;
|
|
u32 lrca_gpu_addr;
|
|
u64 execlist_ctx;
|
|
u32 reserved2[66];
|
|
struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
|
|
} __packed;
|
|
|
|
/**
|
|
* DOC: MMIO based communication
|
|
*
|
|
* The MMIO based communication between Host and GuC uses software scratch
|
|
* registers, where first register holds data treated as message header,
|
|
* and other registers are used to hold message payload.
|
|
*
|
|
* For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8
|
|
*
|
|
* +-----------+---------+---------+---------+
|
|
* | MMIO[0] | MMIO[1] | ... | MMIO[n] |
|
|
* +-----------+---------+---------+---------+
|
|
* | header | optional payload |
|
|
* +======+====+=========+=========+=========+
|
|
* | 31:28|type| | | |
|
|
* +------+----+ | | |
|
|
* | 27:16|data| | | |
|
|
* +------+----+ | | |
|
|
* | 15:0|code| | | |
|
|
* +------+----+---------+---------+---------+
|
|
*
|
|
* The message header consists of:
|
|
*
|
|
* - **type**, indicates message type
|
|
* - **code**, indicates message code, is specific for **type**
|
|
* - **data**, indicates message data, optional, depends on **code**
|
|
*
|
|
* The following message **types** are supported:
|
|
*
|
|
* - **REQUEST**, indicates Host-to-GuC request, requested GuC action code
|
|
* must be priovided in **code** field. Optional action specific parameters
|
|
* can be provided in remaining payload registers or **data** field.
|
|
*
|
|
* - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request,
|
|
* action response status will be provided in **code** field. Optional
|
|
* response data can be returned in remaining payload registers or **data**
|
|
* field.
|
|
*/
|
|
|
|
#define INTEL_GUC_MSG_TYPE_SHIFT 28
|
|
#define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT)
|
|
#define INTEL_GUC_MSG_DATA_SHIFT 16
|
|
#define INTEL_GUC_MSG_DATA_MASK (0xFFF << INTEL_GUC_MSG_DATA_SHIFT)
|
|
#define INTEL_GUC_MSG_CODE_SHIFT 0
|
|
#define INTEL_GUC_MSG_CODE_MASK (0xFFFF << INTEL_GUC_MSG_CODE_SHIFT)
|
|
|
|
#define __INTEL_GUC_MSG_GET(T, m) \
|
|
(((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT)
|
|
#define INTEL_GUC_MSG_TO_TYPE(m) __INTEL_GUC_MSG_GET(TYPE, m)
|
|
#define INTEL_GUC_MSG_TO_DATA(m) __INTEL_GUC_MSG_GET(DATA, m)
|
|
#define INTEL_GUC_MSG_TO_CODE(m) __INTEL_GUC_MSG_GET(CODE, m)
|
|
|
|
enum intel_guc_msg_type {
|
|
INTEL_GUC_MSG_TYPE_REQUEST = 0x0,
|
|
INTEL_GUC_MSG_TYPE_RESPONSE = 0xF,
|
|
};
|
|
|
|
#define __INTEL_GUC_MSG_TYPE_IS(T, m) \
|
|
(INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T)
|
|
#define INTEL_GUC_MSG_IS_REQUEST(m) __INTEL_GUC_MSG_TYPE_IS(REQUEST, m)
|
|
#define INTEL_GUC_MSG_IS_RESPONSE(m) __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m)
|
|
|
|
enum intel_guc_action {
|
|
INTEL_GUC_ACTION_DEFAULT = 0x0,
|
|
INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
|
|
INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
|
|
INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
|
|
INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
|
|
INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
|
|
INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
|
|
INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
|
|
INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
|
|
INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
|
|
INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
|
|
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
|
|
INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
|
|
INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
|
|
INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
|
|
INTEL_GUC_ACTION_LIMIT
|
|
};
|
|
|
|
enum intel_guc_preempt_options {
|
|
INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,
|
|
INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
|
|
};
|
|
|
|
enum intel_guc_report_status {
|
|
INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0,
|
|
INTEL_GUC_REPORT_STATUS_ACKED = 0x1,
|
|
INTEL_GUC_REPORT_STATUS_ERROR = 0x2,
|
|
INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
|
|
};
|
|
|
|
#define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0)
|
|
#define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4
|
|
#define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
|
|
#define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8)
|
|
|
|
enum intel_guc_response_status {
|
|
INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
|
|
INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
|
|
};
|
|
|
|
#define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \
|
|
(typecheck(u32, (m)) && \
|
|
((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \
|
|
((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \
|
|
(INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT)))
|
|
|
|
/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
|
|
enum intel_guc_recv_message {
|
|
INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
|
|
INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)
|
|
};
|
|
|
|
#endif
|