163 lines
3.9 KiB
C
Executable file
163 lines
3.9 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
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#ifndef _A6XX_GMU_H_
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#define _A6XX_GMU_H_
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#include <linux/interrupt.h>
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#include "msm_drv.h"
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#include "a6xx_hfi.h"
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struct a6xx_gmu_bo {
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void *virt;
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size_t size;
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u64 iova;
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struct page **pages;
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};
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/*
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* These define the different GMU wake up options - these define how both the
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* CPU and the GMU bring up the hardware
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*/
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/* THe GMU has already been booted and the rentention registers are active */
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#define GMU_WARM_BOOT 0
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/* the GMU is coming up for the first time or back from a power collapse */
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#define GMU_COLD_BOOT 1
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/* The GMU is being soft reset after a fault */
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#define GMU_RESET 2
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/*
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* These define the level of control that the GMU has - the higher the number
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* the more things that the GMU hardware controls on its own.
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*/
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/* The GMU does not do any idle state management */
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#define GMU_IDLE_STATE_ACTIVE 0
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/* The GMU manages SPTP power collapse */
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#define GMU_IDLE_STATE_SPTP 2
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/* The GMU does automatic IFPC (intra-frame power collapse) */
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#define GMU_IDLE_STATE_IFPC 3
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struct a6xx_gmu {
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struct device *dev;
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void * __iomem mmio;
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void * __iomem pdc_mmio;
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int hfi_irq;
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int gmu_irq;
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struct regulator *gx;
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struct iommu_domain *domain;
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u64 uncached_iova_base;
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int idle_level;
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struct a6xx_gmu_bo *hfi;
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struct a6xx_gmu_bo *debug;
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int nr_clocks;
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struct clk_bulk_data *clocks;
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struct clk *core_clk;
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int nr_gpu_freqs;
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unsigned long gpu_freqs[16];
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u32 gx_arc_votes[16];
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int nr_gmu_freqs;
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unsigned long gmu_freqs[4];
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u32 cx_arc_votes[4];
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struct a6xx_hfi_queue queues[2];
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struct tasklet_struct hfi_tasklet;
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};
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static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
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{
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return msm_readl(gmu->mmio + (offset << 2));
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}
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static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
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{
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return msm_writel(value, gmu->mmio + (offset << 2));
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}
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static inline void pdc_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
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{
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return msm_writel(value, gmu->pdc_mmio + (offset << 2));
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}
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static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
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{
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u32 val = gmu_read(gmu, reg);
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val &= ~mask;
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gmu_write(gmu, reg, val | or);
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}
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#define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
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readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
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interval, timeout)
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/*
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* These are the available OOB (out of band requests) to the GMU where "out of
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* band" means that the CPU talks to the GMU directly and not through HFI.
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* Normally this works by writing a ITCM/DTCM register and then triggering a
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* interrupt (the "request" bit) and waiting for an acknowledgment (the "ack"
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* bit). The state is cleared by writing the "clear' bit to the GMU interrupt.
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*
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* These are used to force the GMU/GPU to stay on during a critical sequence or
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* for hardware workarounds.
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*/
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enum a6xx_gmu_oob_state {
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GMU_OOB_BOOT_SLUMBER = 0,
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GMU_OOB_GPU_SET,
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GMU_OOB_DCVS_SET,
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};
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/* These are the interrupt / ack bits for each OOB request that are set
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* in a6xx_gmu_set_oob and a6xx_clear_oob
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*/
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/*
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* Let the GMU know that a boot or slumber operation has started. The value in
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* REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are
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* doing
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*/
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#define GMU_OOB_BOOT_SLUMBER_REQUEST 22
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#define GMU_OOB_BOOT_SLUMBER_ACK 30
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#define GMU_OOB_BOOT_SLUMBER_CLEAR 30
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/*
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* Set a new power level for the GPU when the CPU is doing frequency scaling
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*/
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#define GMU_OOB_DCVS_REQUEST 23
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#define GMU_OOB_DCVS_ACK 31
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#define GMU_OOB_DCVS_CLEAR 31
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/*
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* Let the GMU know to not turn off any GPU registers while the CPU is in a
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* critical section
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*/
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#define GMU_OOB_GPU_SET_REQUEST 16
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#define GMU_OOB_GPU_SET_ACK 24
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#define GMU_OOB_GPU_SET_CLEAR 24
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void a6xx_hfi_init(struct a6xx_gmu *gmu);
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int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
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void a6xx_hfi_stop(struct a6xx_gmu *gmu);
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void a6xx_hfi_task(unsigned long data);
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#endif
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