471 lines
12 KiB
C
Executable file
471 lines
12 KiB
C
Executable file
/*
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/pm_runtime.h>
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#include "vc4_drv.h"
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#include "vc4_regs.h"
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#ifdef CONFIG_DEBUG_FS
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#define REGDEF(reg) { reg, #reg }
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static const struct {
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uint32_t reg;
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const char *name;
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} vc4_reg_defs[] = {
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REGDEF(V3D_IDENT0),
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REGDEF(V3D_IDENT1),
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REGDEF(V3D_IDENT2),
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REGDEF(V3D_SCRATCH),
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REGDEF(V3D_L2CACTL),
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REGDEF(V3D_SLCACTL),
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REGDEF(V3D_INTCTL),
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REGDEF(V3D_INTENA),
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REGDEF(V3D_INTDIS),
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REGDEF(V3D_CT0CS),
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REGDEF(V3D_CT1CS),
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REGDEF(V3D_CT0EA),
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REGDEF(V3D_CT1EA),
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REGDEF(V3D_CT0CA),
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REGDEF(V3D_CT1CA),
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REGDEF(V3D_CT00RA0),
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REGDEF(V3D_CT01RA0),
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REGDEF(V3D_CT0LC),
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REGDEF(V3D_CT1LC),
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REGDEF(V3D_CT0PC),
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REGDEF(V3D_CT1PC),
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REGDEF(V3D_PCS),
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REGDEF(V3D_BFC),
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REGDEF(V3D_RFC),
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REGDEF(V3D_BPCA),
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REGDEF(V3D_BPCS),
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REGDEF(V3D_BPOA),
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REGDEF(V3D_BPOS),
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REGDEF(V3D_BXCF),
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REGDEF(V3D_SQRSV0),
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REGDEF(V3D_SQRSV1),
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REGDEF(V3D_SQCNTL),
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REGDEF(V3D_SRQPC),
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REGDEF(V3D_SRQUA),
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REGDEF(V3D_SRQUL),
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REGDEF(V3D_SRQCS),
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REGDEF(V3D_VPACNTL),
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REGDEF(V3D_VPMBASE),
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REGDEF(V3D_PCTRC),
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REGDEF(V3D_PCTRE),
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REGDEF(V3D_PCTR(0)),
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REGDEF(V3D_PCTRS(0)),
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REGDEF(V3D_PCTR(1)),
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REGDEF(V3D_PCTRS(1)),
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REGDEF(V3D_PCTR(2)),
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REGDEF(V3D_PCTRS(2)),
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REGDEF(V3D_PCTR(3)),
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REGDEF(V3D_PCTRS(3)),
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REGDEF(V3D_PCTR(4)),
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REGDEF(V3D_PCTRS(4)),
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REGDEF(V3D_PCTR(5)),
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REGDEF(V3D_PCTRS(5)),
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REGDEF(V3D_PCTR(6)),
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REGDEF(V3D_PCTRS(6)),
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REGDEF(V3D_PCTR(7)),
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REGDEF(V3D_PCTRS(7)),
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REGDEF(V3D_PCTR(8)),
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REGDEF(V3D_PCTRS(8)),
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REGDEF(V3D_PCTR(9)),
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REGDEF(V3D_PCTRS(9)),
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REGDEF(V3D_PCTR(10)),
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REGDEF(V3D_PCTRS(10)),
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REGDEF(V3D_PCTR(11)),
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REGDEF(V3D_PCTRS(11)),
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REGDEF(V3D_PCTR(12)),
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REGDEF(V3D_PCTRS(12)),
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REGDEF(V3D_PCTR(13)),
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REGDEF(V3D_PCTRS(13)),
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REGDEF(V3D_PCTR(14)),
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REGDEF(V3D_PCTRS(14)),
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REGDEF(V3D_PCTR(15)),
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REGDEF(V3D_PCTRS(15)),
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REGDEF(V3D_DBGE),
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REGDEF(V3D_FDBGO),
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REGDEF(V3D_FDBGB),
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REGDEF(V3D_FDBGR),
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REGDEF(V3D_FDBGS),
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REGDEF(V3D_ERRSTAT),
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};
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int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused)
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{
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struct drm_info_node *node = (struct drm_info_node *)m->private;
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struct drm_device *dev = node->minor->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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int i;
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for (i = 0; i < ARRAY_SIZE(vc4_reg_defs); i++) {
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seq_printf(m, "%s (0x%04x): 0x%08x\n",
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vc4_reg_defs[i].name, vc4_reg_defs[i].reg,
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V3D_READ(vc4_reg_defs[i].reg));
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}
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return 0;
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}
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int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused)
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{
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struct drm_info_node *node = (struct drm_info_node *)m->private;
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struct drm_device *dev = node->minor->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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uint32_t ident1 = V3D_READ(V3D_IDENT1);
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uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC);
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uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS);
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uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS);
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seq_printf(m, "Revision: %d\n",
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VC4_GET_FIELD(ident1, V3D_IDENT1_REV));
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seq_printf(m, "Slices: %d\n", nslc);
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seq_printf(m, "TMUs: %d\n", nslc * tups);
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seq_printf(m, "QPUs: %d\n", nslc * qups);
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seq_printf(m, "Semaphores: %d\n",
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VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM));
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return 0;
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}
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#endif /* CONFIG_DEBUG_FS */
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static void vc4_v3d_init_hw(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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/* Take all the memory that would have been reserved for user
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* QPU programs, since we don't have an interface for running
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* them, anyway.
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*/
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V3D_WRITE(V3D_VPMBASE, 0);
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}
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int vc4_v3d_get_bin_slot(struct vc4_dev *vc4)
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{
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struct drm_device *dev = vc4->dev;
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unsigned long irqflags;
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int slot;
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uint64_t seqno = 0;
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struct vc4_exec_info *exec;
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try_again:
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spin_lock_irqsave(&vc4->job_lock, irqflags);
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slot = ffs(~vc4->bin_alloc_used);
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if (slot != 0) {
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/* Switch from ffs() bit index to a 0-based index. */
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slot--;
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vc4->bin_alloc_used |= BIT(slot);
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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return slot;
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}
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/* Couldn't find an open slot. Wait for render to complete
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* and try again.
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*/
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exec = vc4_last_render_job(vc4);
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if (exec)
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seqno = exec->seqno;
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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if (seqno) {
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int ret = vc4_wait_for_seqno(dev, seqno, ~0ull, true);
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if (ret == 0)
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goto try_again;
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return ret;
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}
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return -ENOMEM;
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}
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/**
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* vc4_allocate_bin_bo() - allocates the memory that will be used for
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* tile binning.
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*
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* The binner has a limitation that the addresses in the tile state
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* buffer that point into the tile alloc buffer or binner overflow
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* memory only have 28 bits (256MB), and the top 4 on the bus for
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* tile alloc references end up coming from the tile state buffer's
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* address.
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*
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* To work around this, we allocate a single large buffer while V3D is
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* in use, make sure that it has the top 4 bits constant across its
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* entire extent, and then put the tile state, tile alloc, and binner
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* overflow memory inside that buffer.
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*
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* This creates a limitation where we may not be able to execute a job
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* if it doesn't fit within the buffer that we allocated up front.
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* However, it turns out that 16MB is "enough for anybody", and
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* real-world applications run into allocation failures from the
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* overall CMA pool before they make scenes complicated enough to run
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* out of bin space.
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*/
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static int vc4_allocate_bin_bo(struct drm_device *drm)
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{
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struct vc4_dev *vc4 = to_vc4_dev(drm);
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struct vc4_v3d *v3d = vc4->v3d;
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uint32_t size = 16 * 1024 * 1024;
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int ret = 0;
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struct list_head list;
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/* We may need to try allocating more than once to get a BO
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* that doesn't cross 256MB. Track the ones we've allocated
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* that failed so far, so that we can free them when we've got
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* one that succeeded (if we freed them right away, our next
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* allocation would probably be the same chunk of memory).
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*/
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INIT_LIST_HEAD(&list);
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while (true) {
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struct vc4_bo *bo = vc4_bo_create(drm, size, true,
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VC4_BO_TYPE_BIN);
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if (IS_ERR(bo)) {
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ret = PTR_ERR(bo);
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dev_err(&v3d->pdev->dev,
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"Failed to allocate memory for tile binning: "
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"%d. You may need to enable CMA or give it "
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"more memory.",
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ret);
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break;
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}
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/* Check if this BO won't trigger the addressing bug. */
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if ((bo->base.paddr & 0xf0000000) ==
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((bo->base.paddr + bo->base.base.size - 1) & 0xf0000000)) {
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vc4->bin_bo = bo;
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/* Set up for allocating 512KB chunks of
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* binner memory. The biggest allocation we
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* need to do is for the initial tile alloc +
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* tile state buffer. We can render to a
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* maximum of ((2048*2048) / (32*32) = 4096
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* tiles in a frame (until we do floating
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* point rendering, at which point it would be
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* 8192). Tile state is 48b/tile (rounded to
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* a page), and tile alloc is 32b/tile
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* (rounded to a page), plus a page of extra,
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* for a total of 320kb for our worst-case.
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* We choose 512kb so that it divides evenly
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* into our 16MB, and the rest of the 512kb
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* will be used as storage for the overflow
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* from the initial 32b CL per bin.
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*/
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vc4->bin_alloc_size = 512 * 1024;
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vc4->bin_alloc_used = 0;
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vc4->bin_alloc_overflow = 0;
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WARN_ON_ONCE(sizeof(vc4->bin_alloc_used) * 8 !=
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bo->base.base.size / vc4->bin_alloc_size);
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break;
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}
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/* Put it on the list to free later, and try again. */
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list_add(&bo->unref_head, &list);
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}
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/* Free all the BOs we allocated but didn't choose. */
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while (!list_empty(&list)) {
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struct vc4_bo *bo = list_last_entry(&list,
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struct vc4_bo, unref_head);
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list_del(&bo->unref_head);
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drm_gem_object_put_unlocked(&bo->base.base);
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}
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return ret;
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}
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#ifdef CONFIG_PM
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static int vc4_v3d_runtime_suspend(struct device *dev)
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{
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struct vc4_v3d *v3d = dev_get_drvdata(dev);
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struct vc4_dev *vc4 = v3d->vc4;
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vc4_irq_uninstall(vc4->dev);
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drm_gem_object_put_unlocked(&vc4->bin_bo->base.base);
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vc4->bin_bo = NULL;
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clk_disable_unprepare(v3d->clk);
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return 0;
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}
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static int vc4_v3d_runtime_resume(struct device *dev)
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{
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struct vc4_v3d *v3d = dev_get_drvdata(dev);
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struct vc4_dev *vc4 = v3d->vc4;
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int ret;
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ret = vc4_allocate_bin_bo(vc4->dev);
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if (ret)
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return ret;
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ret = clk_prepare_enable(v3d->clk);
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if (ret != 0)
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return ret;
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vc4_v3d_init_hw(vc4->dev);
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/* We disabled the IRQ as part of vc4_irq_uninstall in suspend. */
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enable_irq(vc4->dev->irq);
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vc4_irq_postinstall(vc4->dev);
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return 0;
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}
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#endif
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static int vc4_v3d_bind(struct device *dev, struct device *master, void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct drm_device *drm = dev_get_drvdata(master);
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struct vc4_dev *vc4 = to_vc4_dev(drm);
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struct vc4_v3d *v3d = NULL;
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int ret;
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v3d = devm_kzalloc(&pdev->dev, sizeof(*v3d), GFP_KERNEL);
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if (!v3d)
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return -ENOMEM;
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dev_set_drvdata(dev, v3d);
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v3d->pdev = pdev;
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v3d->regs = vc4_ioremap_regs(pdev, 0);
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if (IS_ERR(v3d->regs))
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return PTR_ERR(v3d->regs);
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vc4->v3d = v3d;
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v3d->vc4 = vc4;
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v3d->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(v3d->clk)) {
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int ret = PTR_ERR(v3d->clk);
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if (ret == -ENOENT) {
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/* bcm2835 didn't have a clock reference in the DT. */
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ret = 0;
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v3d->clk = NULL;
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} else {
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "Failed to get V3D clock: %d\n",
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ret);
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return ret;
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}
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}
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if (V3D_READ(V3D_IDENT0) != V3D_EXPECTED_IDENT0) {
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DRM_ERROR("V3D_IDENT0 read 0x%08x instead of 0x%08x\n",
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V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0);
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return -EINVAL;
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}
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ret = clk_prepare_enable(v3d->clk);
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if (ret != 0)
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return ret;
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ret = vc4_allocate_bin_bo(drm);
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if (ret) {
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clk_disable_unprepare(v3d->clk);
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return ret;
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}
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/* Reset the binner overflow address/size at setup, to be sure
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* we don't reuse an old one.
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*/
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V3D_WRITE(V3D_BPOA, 0);
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V3D_WRITE(V3D_BPOS, 0);
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vc4_v3d_init_hw(drm);
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ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
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if (ret) {
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DRM_ERROR("Failed to install IRQ handler\n");
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return ret;
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}
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pm_runtime_set_active(dev);
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pm_runtime_use_autosuspend(dev);
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pm_runtime_set_autosuspend_delay(dev, 40); /* a little over 2 frames. */
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pm_runtime_enable(dev);
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return 0;
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}
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static void vc4_v3d_unbind(struct device *dev, struct device *master,
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void *data)
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{
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struct drm_device *drm = dev_get_drvdata(master);
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struct vc4_dev *vc4 = to_vc4_dev(drm);
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pm_runtime_disable(dev);
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drm_irq_uninstall(drm);
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/* Disable the binner's overflow memory address, so the next
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* driver probe (if any) doesn't try to reuse our old
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* allocation.
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*/
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V3D_WRITE(V3D_BPOA, 0);
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V3D_WRITE(V3D_BPOS, 0);
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vc4->v3d = NULL;
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}
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static const struct dev_pm_ops vc4_v3d_pm_ops = {
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SET_RUNTIME_PM_OPS(vc4_v3d_runtime_suspend, vc4_v3d_runtime_resume, NULL)
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};
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static const struct component_ops vc4_v3d_ops = {
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.bind = vc4_v3d_bind,
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.unbind = vc4_v3d_unbind,
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};
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static int vc4_v3d_dev_probe(struct platform_device *pdev)
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{
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return component_add(&pdev->dev, &vc4_v3d_ops);
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}
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static int vc4_v3d_dev_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &vc4_v3d_ops);
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return 0;
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}
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static const struct of_device_id vc4_v3d_dt_match[] = {
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{ .compatible = "brcm,bcm2835-v3d" },
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{ .compatible = "brcm,cygnus-v3d" },
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{ .compatible = "brcm,vc4-v3d" },
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{}
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};
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struct platform_driver vc4_v3d_driver = {
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.probe = vc4_v3d_dev_probe,
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.remove = vc4_v3d_dev_remove,
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.driver = {
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.name = "vc4_v3d",
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.of_match_table = vc4_v3d_dt_match,
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.pm = &vc4_v3d_pm_ops,
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},
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};
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