670 lines
18 KiB
C
Executable file
670 lines
18 KiB
C
Executable file
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2012 FUJITSU SEMICONDUCTOR LIMITED
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*/
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#define WAIT_PCLK(n, rate) \
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ndelay(DIV_ROUND_UP(DIV_ROUND_UP(1000000000, rate), n) + 10)
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/* I2C register address definitions */
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#define SYNQUACER_I2C_REG_BSR (0x00 << 2) // Bus Status
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#define SYNQUACER_I2C_REG_BCR (0x01 << 2) // Bus Control
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#define SYNQUACER_I2C_REG_CCR (0x02 << 2) // Clock Control
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#define SYNQUACER_I2C_REG_ADR (0x03 << 2) // Address
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#define SYNQUACER_I2C_REG_DAR (0x04 << 2) // Data
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#define SYNQUACER_I2C_REG_CSR (0x05 << 2) // Expansion CS
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#define SYNQUACER_I2C_REG_FSR (0x06 << 2) // Bus Clock Freq
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#define SYNQUACER_I2C_REG_BC2R (0x07 << 2) // Bus Control 2
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/* I2C register bit definitions */
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#define SYNQUACER_I2C_BSR_FBT BIT(0) // First Byte Transfer
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#define SYNQUACER_I2C_BSR_GCA BIT(1) // General Call Address
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#define SYNQUACER_I2C_BSR_AAS BIT(2) // Address as Slave
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#define SYNQUACER_I2C_BSR_TRX BIT(3) // Transfer/Receive
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#define SYNQUACER_I2C_BSR_LRB BIT(4) // Last Received Bit
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#define SYNQUACER_I2C_BSR_AL BIT(5) // Arbitration Lost
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#define SYNQUACER_I2C_BSR_RSC BIT(6) // Repeated Start Cond.
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#define SYNQUACER_I2C_BSR_BB BIT(7) // Bus Busy
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#define SYNQUACER_I2C_BCR_INT BIT(0) // Interrupt
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#define SYNQUACER_I2C_BCR_INTE BIT(1) // Interrupt Enable
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#define SYNQUACER_I2C_BCR_GCAA BIT(2) // Gen. Call Access Ack.
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#define SYNQUACER_I2C_BCR_ACK BIT(3) // Acknowledge
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#define SYNQUACER_I2C_BCR_MSS BIT(4) // Master Slave Select
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#define SYNQUACER_I2C_BCR_SCC BIT(5) // Start Condition Cont.
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#define SYNQUACER_I2C_BCR_BEIE BIT(6) // Bus Error Int Enable
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#define SYNQUACER_I2C_BCR_BER BIT(7) // Bus Error
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#define SYNQUACER_I2C_CCR_CS_MASK (0x1f) // CCR Clock Period Sel.
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#define SYNQUACER_I2C_CCR_EN BIT(5) // Enable
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#define SYNQUACER_I2C_CCR_FM BIT(6) // Speed Mode Select
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#define SYNQUACER_I2C_CSR_CS_MASK (0x3f) // CSR Clock Period Sel.
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#define SYNQUACER_I2C_BC2R_SCLL BIT(0) // SCL Low Drive
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#define SYNQUACER_I2C_BC2R_SDAL BIT(1) // SDA Low Drive
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#define SYNQUACER_I2C_BC2R_SCLS BIT(4) // SCL Status
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#define SYNQUACER_I2C_BC2R_SDAS BIT(5) // SDA Status
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/* PCLK frequency */
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#define SYNQUACER_I2C_BUS_CLK_FR(rate) (((rate) / 20000000) + 1)
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/* STANDARD MODE frequency */
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#define SYNQUACER_I2C_CLK_MASTER_STD(rate) \
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DIV_ROUND_UP(DIV_ROUND_UP((rate), 100000) - 2, 2)
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/* FAST MODE frequency */
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#define SYNQUACER_I2C_CLK_MASTER_FAST(rate) \
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DIV_ROUND_UP((DIV_ROUND_UP((rate), 400000) - 2) * 2, 3)
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/* (clkrate <= 18000000) */
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/* calculate the value of CS bits in CCR register on standard mode */
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#define SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rate) \
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((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \
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& SYNQUACER_I2C_CCR_CS_MASK)
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/* calculate the value of CS bits in CSR register on standard mode */
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#define SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rate) 0x00
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/* calculate the value of CS bits in CCR register on fast mode */
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#define SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rate) \
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((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
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& SYNQUACER_I2C_CCR_CS_MASK)
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/* calculate the value of CS bits in CSR register on fast mode */
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#define SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rate) 0x00
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/* (clkrate > 18000000) */
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/* calculate the value of CS bits in CCR register on standard mode */
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#define SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rate) \
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((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) \
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& SYNQUACER_I2C_CCR_CS_MASK)
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/* calculate the value of CS bits in CSR register on standard mode */
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#define SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rate) \
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(((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) >> 5) \
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& SYNQUACER_I2C_CSR_CS_MASK)
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/* calculate the value of CS bits in CCR register on fast mode */
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#define SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rate) \
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((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
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& SYNQUACER_I2C_CCR_CS_MASK)
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/* calculate the value of CS bits in CSR register on fast mode */
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#define SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rate) \
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(((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) >> 5) \
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& SYNQUACER_I2C_CSR_CS_MASK)
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/* min I2C clock frequency 14M */
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#define SYNQUACER_I2C_MIN_CLK_RATE (14 * 1000000)
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/* max I2C clock frequency 200M */
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#define SYNQUACER_I2C_MAX_CLK_RATE (200 * 1000000)
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/* I2C clock frequency 18M */
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#define SYNQUACER_I2C_CLK_RATE_18M (18 * 1000000)
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#define SYNQUACER_I2C_SPEED_FM 400 // Fast Mode
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#define SYNQUACER_I2C_SPEED_SM 100 // Standard Mode
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enum i2c_state {
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STATE_IDLE,
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STATE_START,
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STATE_READ,
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STATE_WRITE
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};
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struct synquacer_i2c {
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struct completion completion;
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struct i2c_msg *msg;
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u32 msg_num;
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u32 msg_idx;
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u32 msg_ptr;
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int irq;
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struct device *dev;
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void __iomem *base;
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struct clk *pclk;
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u32 pclkrate;
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u32 speed_khz;
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u32 timeout_ms;
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enum i2c_state state;
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struct i2c_adapter adapter;
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bool is_suspended;
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};
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static inline int is_lastmsg(struct synquacer_i2c *i2c)
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{
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return i2c->msg_idx >= (i2c->msg_num - 1);
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}
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static inline int is_msglast(struct synquacer_i2c *i2c)
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{
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return i2c->msg_ptr == (i2c->msg->len - 1);
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}
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static inline int is_msgend(struct synquacer_i2c *i2c)
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{
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return i2c->msg_ptr >= i2c->msg->len;
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}
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static inline unsigned long calc_timeout_ms(struct synquacer_i2c *i2c,
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struct i2c_msg *msgs,
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int num)
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{
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unsigned long bit_count = 0;
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int i;
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for (i = 0; i < num; i++, msgs++)
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bit_count += msgs->len;
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return DIV_ROUND_UP((bit_count * 9 + num * 10) * 3, 200) + 10;
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}
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static void synquacer_i2c_stop(struct synquacer_i2c *i2c, int ret)
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{
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/*
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* clear IRQ (INT=0, BER=0)
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* set Stop Condition (MSS=0)
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* Interrupt Disable
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*/
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writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR);
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i2c->state = STATE_IDLE;
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i2c->msg_ptr = 0;
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i2c->msg = NULL;
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i2c->msg_idx++;
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i2c->msg_num = 0;
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if (ret)
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i2c->msg_idx = ret;
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complete(&i2c->completion);
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}
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static void synquacer_i2c_hw_init(struct synquacer_i2c *i2c)
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{
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unsigned char ccr_cs, csr_cs;
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u32 rt = i2c->pclkrate;
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/* Set own Address */
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writeb(0, i2c->base + SYNQUACER_I2C_REG_ADR);
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/* Set PCLK frequency */
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writeb(SYNQUACER_I2C_BUS_CLK_FR(i2c->pclkrate),
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i2c->base + SYNQUACER_I2C_REG_FSR);
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switch (i2c->speed_khz) {
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case SYNQUACER_I2C_SPEED_FM:
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if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) {
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ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rt);
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csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rt);
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} else {
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ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rt);
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csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rt);
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}
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/* Set Clock and enable, Set fast mode */
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writeb(ccr_cs | SYNQUACER_I2C_CCR_FM |
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SYNQUACER_I2C_CCR_EN,
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i2c->base + SYNQUACER_I2C_REG_CCR);
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writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR);
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break;
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case SYNQUACER_I2C_SPEED_SM:
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if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) {
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ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rt);
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csr_cs = SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rt);
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} else {
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ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rt);
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csr_cs = SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rt);
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}
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/* Set Clock and enable, Set standard mode */
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writeb(ccr_cs | SYNQUACER_I2C_CCR_EN,
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i2c->base + SYNQUACER_I2C_REG_CCR);
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writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR);
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break;
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default:
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WARN_ON(1);
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}
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/* clear IRQ (INT=0, BER=0), Interrupt Disable */
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writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR);
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writeb(0, i2c->base + SYNQUACER_I2C_REG_BC2R);
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}
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static void synquacer_i2c_hw_reset(struct synquacer_i2c *i2c)
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{
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/* Disable clock */
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writeb(0, i2c->base + SYNQUACER_I2C_REG_CCR);
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writeb(0, i2c->base + SYNQUACER_I2C_REG_CSR);
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WAIT_PCLK(100, i2c->pclkrate);
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}
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static int synquacer_i2c_master_start(struct synquacer_i2c *i2c,
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struct i2c_msg *pmsg)
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{
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unsigned char bsr, bcr;
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writeb(i2c_8bit_addr_from_msg(pmsg), i2c->base + SYNQUACER_I2C_REG_DAR);
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dev_dbg(i2c->dev, "slave:0x%02x\n", pmsg->addr);
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/* Generate Start Condition */
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bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
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bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
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dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
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if ((bsr & SYNQUACER_I2C_BSR_BB) &&
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!(bcr & SYNQUACER_I2C_BCR_MSS)) {
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dev_dbg(i2c->dev, "bus is busy");
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return -EBUSY;
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}
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if (bsr & SYNQUACER_I2C_BSR_BB) { /* Bus is busy */
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dev_dbg(i2c->dev, "Continuous Start");
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writeb(bcr | SYNQUACER_I2C_BCR_SCC,
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i2c->base + SYNQUACER_I2C_REG_BCR);
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} else {
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if (bcr & SYNQUACER_I2C_BCR_MSS) {
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dev_dbg(i2c->dev, "not in master mode");
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return -EAGAIN;
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}
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dev_dbg(i2c->dev, "Start Condition");
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/* Start Condition + Enable Interrupts */
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writeb(bcr | SYNQUACER_I2C_BCR_MSS |
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SYNQUACER_I2C_BCR_INTE | SYNQUACER_I2C_BCR_BEIE,
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i2c->base + SYNQUACER_I2C_REG_BCR);
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}
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WAIT_PCLK(10, i2c->pclkrate);
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/* get BSR & BCR registers */
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bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
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bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
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dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
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if ((bsr & SYNQUACER_I2C_BSR_AL) ||
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!(bcr & SYNQUACER_I2C_BCR_MSS)) {
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dev_dbg(i2c->dev, "arbitration lost\n");
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return -EAGAIN;
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}
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return 0;
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}
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static int synquacer_i2c_doxfer(struct synquacer_i2c *i2c,
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struct i2c_msg *msgs, int num)
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{
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unsigned char bsr;
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unsigned long timeout;
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int ret;
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if (i2c->is_suspended)
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return -EBUSY;
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synquacer_i2c_hw_init(i2c);
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bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
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if (bsr & SYNQUACER_I2C_BSR_BB) {
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dev_err(i2c->dev, "cannot get bus (bus busy)\n");
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return -EBUSY;
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}
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reinit_completion(&i2c->completion);
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i2c->msg = msgs;
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i2c->msg_num = num;
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i2c->msg_ptr = 0;
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i2c->msg_idx = 0;
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i2c->state = STATE_START;
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ret = synquacer_i2c_master_start(i2c, i2c->msg);
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if (ret < 0) {
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dev_dbg(i2c->dev, "Address failed: (%d)\n", ret);
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return ret;
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}
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timeout = wait_for_completion_timeout(&i2c->completion,
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msecs_to_jiffies(i2c->timeout_ms));
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if (timeout == 0) {
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dev_dbg(i2c->dev, "timeout\n");
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return -EAGAIN;
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}
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ret = i2c->msg_idx;
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if (ret != num) {
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dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
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return -EAGAIN;
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}
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/* wait 2 clock periods to ensure the stop has been through the bus */
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udelay(DIV_ROUND_UP(2 * 1000, i2c->speed_khz));
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return ret;
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}
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static irqreturn_t synquacer_i2c_isr(int irq, void *dev_id)
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{
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struct synquacer_i2c *i2c = dev_id;
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unsigned char byte;
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unsigned char bsr, bcr;
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int ret;
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bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
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bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
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dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
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if (bcr & SYNQUACER_I2C_BCR_BER) {
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dev_err(i2c->dev, "bus error\n");
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synquacer_i2c_stop(i2c, -EAGAIN);
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goto out;
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}
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if ((bsr & SYNQUACER_I2C_BSR_AL) ||
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!(bcr & SYNQUACER_I2C_BCR_MSS)) {
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dev_dbg(i2c->dev, "arbitration lost\n");
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synquacer_i2c_stop(i2c, -EAGAIN);
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goto out;
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}
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switch (i2c->state) {
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case STATE_START:
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if (bsr & SYNQUACER_I2C_BSR_LRB) {
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dev_dbg(i2c->dev, "ack was not received\n");
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synquacer_i2c_stop(i2c, -EAGAIN);
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goto out;
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}
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if (i2c->msg->flags & I2C_M_RD)
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i2c->state = STATE_READ;
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else
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i2c->state = STATE_WRITE;
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if (is_lastmsg(i2c) && i2c->msg->len == 0) {
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synquacer_i2c_stop(i2c, 0);
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goto out;
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}
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if (i2c->state == STATE_READ)
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goto prepare_read;
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/* fallthru */
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case STATE_WRITE:
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if (bsr & SYNQUACER_I2C_BSR_LRB) {
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dev_dbg(i2c->dev, "WRITE: No Ack\n");
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synquacer_i2c_stop(i2c, -EAGAIN);
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goto out;
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}
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if (!is_msgend(i2c)) {
|
|
writeb(i2c->msg->buf[i2c->msg_ptr++],
|
|
i2c->base + SYNQUACER_I2C_REG_DAR);
|
|
|
|
/* clear IRQ, and continue */
|
|
writeb(SYNQUACER_I2C_BCR_BEIE |
|
|
SYNQUACER_I2C_BCR_MSS |
|
|
SYNQUACER_I2C_BCR_INTE,
|
|
i2c->base + SYNQUACER_I2C_REG_BCR);
|
|
break;
|
|
}
|
|
if (is_lastmsg(i2c)) {
|
|
synquacer_i2c_stop(i2c, 0);
|
|
break;
|
|
}
|
|
dev_dbg(i2c->dev, "WRITE: Next Message\n");
|
|
|
|
i2c->msg_ptr = 0;
|
|
i2c->msg_idx++;
|
|
i2c->msg++;
|
|
|
|
/* send the new start */
|
|
ret = synquacer_i2c_master_start(i2c, i2c->msg);
|
|
if (ret < 0) {
|
|
dev_dbg(i2c->dev, "restart error (%d)\n", ret);
|
|
synquacer_i2c_stop(i2c, -EAGAIN);
|
|
break;
|
|
}
|
|
i2c->state = STATE_START;
|
|
break;
|
|
|
|
case STATE_READ:
|
|
byte = readb(i2c->base + SYNQUACER_I2C_REG_DAR);
|
|
if (!(bsr & SYNQUACER_I2C_BSR_FBT)) /* data */
|
|
i2c->msg->buf[i2c->msg_ptr++] = byte;
|
|
else /* address */
|
|
dev_dbg(i2c->dev, "address:0x%02x. ignore it.\n", byte);
|
|
|
|
prepare_read:
|
|
if (is_msglast(i2c)) {
|
|
writeb(SYNQUACER_I2C_BCR_MSS |
|
|
SYNQUACER_I2C_BCR_BEIE |
|
|
SYNQUACER_I2C_BCR_INTE,
|
|
i2c->base + SYNQUACER_I2C_REG_BCR);
|
|
break;
|
|
}
|
|
if (!is_msgend(i2c)) {
|
|
writeb(SYNQUACER_I2C_BCR_MSS |
|
|
SYNQUACER_I2C_BCR_BEIE |
|
|
SYNQUACER_I2C_BCR_INTE |
|
|
SYNQUACER_I2C_BCR_ACK,
|
|
i2c->base + SYNQUACER_I2C_REG_BCR);
|
|
break;
|
|
}
|
|
if (is_lastmsg(i2c)) {
|
|
/* last message, send stop and complete */
|
|
dev_dbg(i2c->dev, "READ: Send Stop\n");
|
|
synquacer_i2c_stop(i2c, 0);
|
|
break;
|
|
}
|
|
dev_dbg(i2c->dev, "READ: Next Transfer\n");
|
|
|
|
i2c->msg_ptr = 0;
|
|
i2c->msg_idx++;
|
|
i2c->msg++;
|
|
|
|
ret = synquacer_i2c_master_start(i2c, i2c->msg);
|
|
if (ret < 0) {
|
|
dev_dbg(i2c->dev, "restart error (%d)\n", ret);
|
|
synquacer_i2c_stop(i2c, -EAGAIN);
|
|
} else {
|
|
i2c->state = STATE_START;
|
|
}
|
|
break;
|
|
default:
|
|
dev_err(i2c->dev, "called in err STATE (%d)\n", i2c->state);
|
|
break;
|
|
}
|
|
|
|
out:
|
|
WAIT_PCLK(10, i2c->pclkrate);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int synquacer_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
|
|
int num)
|
|
{
|
|
struct synquacer_i2c *i2c;
|
|
int retry;
|
|
int ret;
|
|
|
|
i2c = i2c_get_adapdata(adap);
|
|
i2c->timeout_ms = calc_timeout_ms(i2c, msgs, num);
|
|
|
|
dev_dbg(i2c->dev, "calculated timeout %d ms\n", i2c->timeout_ms);
|
|
|
|
for (retry = 0; retry <= adap->retries; retry++) {
|
|
ret = synquacer_i2c_doxfer(i2c, msgs, num);
|
|
if (ret != -EAGAIN)
|
|
return ret;
|
|
|
|
dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
|
|
|
|
synquacer_i2c_hw_reset(i2c);
|
|
}
|
|
return -EIO;
|
|
}
|
|
|
|
static u32 synquacer_i2c_functionality(struct i2c_adapter *adap)
|
|
{
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
|
}
|
|
|
|
static const struct i2c_algorithm synquacer_i2c_algo = {
|
|
.master_xfer = synquacer_i2c_xfer,
|
|
.functionality = synquacer_i2c_functionality,
|
|
};
|
|
|
|
static struct i2c_adapter synquacer_i2c_ops = {
|
|
.owner = THIS_MODULE,
|
|
.name = "synquacer_i2c-adapter",
|
|
.algo = &synquacer_i2c_algo,
|
|
.retries = 5,
|
|
};
|
|
|
|
static int synquacer_i2c_probe(struct platform_device *pdev)
|
|
{
|
|
struct synquacer_i2c *i2c;
|
|
struct resource *r;
|
|
u32 bus_speed;
|
|
int ret;
|
|
|
|
i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
|
|
if (!i2c)
|
|
return -ENOMEM;
|
|
|
|
bus_speed = i2c_acpi_find_bus_speed(&pdev->dev);
|
|
if (!bus_speed)
|
|
device_property_read_u32(&pdev->dev, "clock-frequency",
|
|
&bus_speed);
|
|
|
|
device_property_read_u32(&pdev->dev, "socionext,pclk-rate",
|
|
&i2c->pclkrate);
|
|
|
|
i2c->pclk = devm_clk_get(&pdev->dev, "pclk");
|
|
if (IS_ERR(i2c->pclk) && PTR_ERR(i2c->pclk) == -EPROBE_DEFER)
|
|
return -EPROBE_DEFER;
|
|
if (!IS_ERR_OR_NULL(i2c->pclk)) {
|
|
dev_dbg(&pdev->dev, "clock source %p\n", i2c->pclk);
|
|
|
|
ret = clk_prepare_enable(i2c->pclk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to enable clock (%d)\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
i2c->pclkrate = clk_get_rate(i2c->pclk);
|
|
}
|
|
|
|
if (i2c->pclkrate < SYNQUACER_I2C_MIN_CLK_RATE ||
|
|
i2c->pclkrate > SYNQUACER_I2C_MAX_CLK_RATE) {
|
|
dev_err(&pdev->dev, "PCLK missing or out of range (%d)\n",
|
|
i2c->pclkrate);
|
|
return -EINVAL;
|
|
}
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
i2c->base = devm_ioremap_resource(&pdev->dev, r);
|
|
if (IS_ERR(i2c->base))
|
|
return PTR_ERR(i2c->base);
|
|
|
|
i2c->irq = platform_get_irq(pdev, 0);
|
|
if (i2c->irq < 0) {
|
|
dev_err(&pdev->dev, "no IRQ resource found\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, i2c->irq, synquacer_i2c_isr,
|
|
0, dev_name(&pdev->dev), i2c);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
|
|
return ret;
|
|
}
|
|
|
|
i2c->state = STATE_IDLE;
|
|
i2c->dev = &pdev->dev;
|
|
i2c->adapter = synquacer_i2c_ops;
|
|
i2c_set_adapdata(&i2c->adapter, i2c);
|
|
i2c->adapter.dev.parent = &pdev->dev;
|
|
i2c->adapter.dev.of_node = pdev->dev.of_node;
|
|
ACPI_COMPANION_SET(&i2c->adapter.dev, ACPI_COMPANION(&pdev->dev));
|
|
i2c->adapter.nr = pdev->id;
|
|
init_completion(&i2c->completion);
|
|
|
|
if (bus_speed < 400000)
|
|
i2c->speed_khz = SYNQUACER_I2C_SPEED_SM;
|
|
else
|
|
i2c->speed_khz = SYNQUACER_I2C_SPEED_FM;
|
|
|
|
synquacer_i2c_hw_init(i2c);
|
|
|
|
ret = i2c_add_numbered_adapter(&i2c->adapter);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to add bus to i2c core\n");
|
|
return ret;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, i2c);
|
|
|
|
dev_info(&pdev->dev, "%s: synquacer_i2c adapter\n",
|
|
dev_name(&i2c->adapter.dev));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int synquacer_i2c_remove(struct platform_device *pdev)
|
|
{
|
|
struct synquacer_i2c *i2c = platform_get_drvdata(pdev);
|
|
|
|
i2c_del_adapter(&i2c->adapter);
|
|
if (!IS_ERR(i2c->pclk))
|
|
clk_disable_unprepare(i2c->pclk);
|
|
|
|
return 0;
|
|
};
|
|
|
|
static const struct of_device_id synquacer_i2c_dt_ids[] = {
|
|
{ .compatible = "socionext,synquacer-i2c" },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, synquacer_i2c_dt_ids);
|
|
|
|
#ifdef CONFIG_ACPI
|
|
static const struct acpi_device_id synquacer_i2c_acpi_ids[] = {
|
|
{ "SCX0003" },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, synquacer_i2c_acpi_ids);
|
|
#endif
|
|
|
|
static struct platform_driver synquacer_i2c_driver = {
|
|
.probe = synquacer_i2c_probe,
|
|
.remove = synquacer_i2c_remove,
|
|
.driver = {
|
|
.name = "synquacer_i2c",
|
|
.of_match_table = of_match_ptr(synquacer_i2c_dt_ids),
|
|
.acpi_match_table = ACPI_PTR(synquacer_i2c_acpi_ids),
|
|
},
|
|
};
|
|
module_platform_driver(synquacer_i2c_driver);
|
|
|
|
MODULE_AUTHOR("Fujitsu Semiconductor Ltd");
|
|
MODULE_DESCRIPTION("Socionext SynQuacer I2C Driver");
|
|
MODULE_LICENSE("GPL v2");
|