584 lines
18 KiB
C
Executable file
584 lines
18 KiB
C
Executable file
/*
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* Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
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* Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __NES_H
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#define __NES_H
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#include <linux/netdevice.h>
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#include <linux/inetdevice.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/workqueue.h>
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#include <linux/slab.h>
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#include <asm/io.h>
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#include <linux/crc32c.h>
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#include <rdma/ib_smi.h>
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#include <rdma/ib_verbs.h>
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#include <rdma/ib_pack.h>
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#include <rdma/rdma_cm.h>
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#include <rdma/iw_cm.h>
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#include <rdma/rdma_netlink.h>
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#include <rdma/iw_portmap.h>
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#define NES_SEND_FIRST_WRITE
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#define QUEUE_DISCONNECTS
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#define DRV_NAME "iw_nes"
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#define DRV_VERSION "1.5.0.1"
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#define PFX DRV_NAME ": "
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/*
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* NetEffect PCI vendor id and NE010 PCI device id.
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*/
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#ifndef PCI_VENDOR_ID_NETEFFECT /* not in pci.ids yet */
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#define PCI_VENDOR_ID_NETEFFECT 0x1678
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#define PCI_DEVICE_ID_NETEFFECT_NE020 0x0100
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#define PCI_DEVICE_ID_NETEFFECT_NE020_KR 0x0110
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#endif
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#define NE020_REV 4
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#define NE020_REV1 5
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#define BAR_0 0
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#define BAR_1 2
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#define RX_BUF_SIZE (1536 + 8)
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#define NES_REG0_SIZE (4 * 1024)
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#define NES_TX_TIMEOUT (6*HZ)
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#define NES_FIRST_QPN 64
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#define NES_SW_CONTEXT_ALIGN 1024
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#define NES_MAX_MTU 9000
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#define NES_NIC_MAX_NICS 16
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#define NES_MAX_ARP_TABLE_SIZE 4096
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#define NES_NIC_CEQ_SIZE 8
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/* NICs will be on a separate CQ */
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#define NES_CCEQ_SIZE ((nesadapter->max_cq / nesadapter->port_count) - 32)
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#define NES_MAX_PORT_COUNT 4
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#define MAX_DPC_ITERATIONS 128
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#define NES_DRV_OPT_ENABLE_MPA_VER_0 0x00000001
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#define NES_DRV_OPT_DISABLE_MPA_CRC 0x00000002
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#define NES_DRV_OPT_DISABLE_FIRST_WRITE 0x00000004
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#define NES_DRV_OPT_DISABLE_INTF 0x00000008
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#define NES_DRV_OPT_ENABLE_MSI 0x00000010
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#define NES_DRV_OPT_DUAL_LOGICAL_PORT 0x00000020
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#define NES_DRV_OPT_SUPRESS_OPTION_BC 0x00000040
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#define NES_DRV_OPT_NO_INLINE_DATA 0x00000080
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#define NES_DRV_OPT_DISABLE_INT_MOD 0x00000100
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#define NES_DRV_OPT_DISABLE_VIRT_WQ 0x00000200
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#define NES_DRV_OPT_ENABLE_PAU 0x00000400
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#define NES_AEQ_EVENT_TIMEOUT 2500
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#define NES_DISCONNECT_EVENT_TIMEOUT 2000
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/* debug levels */
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/* must match userspace */
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#define NES_DBG_HW 0x00000001
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#define NES_DBG_INIT 0x00000002
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#define NES_DBG_ISR 0x00000004
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#define NES_DBG_PHY 0x00000008
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#define NES_DBG_NETDEV 0x00000010
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#define NES_DBG_CM 0x00000020
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#define NES_DBG_CM1 0x00000040
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#define NES_DBG_NIC_RX 0x00000080
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#define NES_DBG_NIC_TX 0x00000100
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#define NES_DBG_CQP 0x00000200
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#define NES_DBG_MMAP 0x00000400
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#define NES_DBG_MR 0x00000800
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#define NES_DBG_PD 0x00001000
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#define NES_DBG_CQ 0x00002000
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#define NES_DBG_QP 0x00004000
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#define NES_DBG_MOD_QP 0x00008000
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#define NES_DBG_AEQ 0x00010000
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#define NES_DBG_IW_RX 0x00020000
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#define NES_DBG_IW_TX 0x00040000
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#define NES_DBG_SHUTDOWN 0x00080000
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#define NES_DBG_PAU 0x00100000
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#define NES_DBG_NLMSG 0x00200000
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#define NES_DBG_RSVD1 0x10000000
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#define NES_DBG_RSVD2 0x20000000
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#define NES_DBG_RSVD3 0x40000000
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#define NES_DBG_RSVD4 0x80000000
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#define NES_DBG_ALL 0xffffffff
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#ifdef CONFIG_INFINIBAND_NES_DEBUG
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#define nes_debug(level, fmt, args...) \
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do { \
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if (level & nes_debug_level) \
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printk(KERN_ERR PFX "%s[%u]: " fmt, __func__, __LINE__, ##args); \
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} while (0)
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#define assert(expr) \
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do { \
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if (!(expr)) { \
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printk(KERN_ERR PFX "Assertion failed! %s, %s, %s, line %d\n", \
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#expr, __FILE__, __func__, __LINE__); \
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} \
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} while (0)
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#define NES_EVENT_TIMEOUT 1200000
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#else
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#define nes_debug(level, fmt, args...) no_printk(fmt, ##args)
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#define assert(expr) do {} while (0)
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#define NES_EVENT_TIMEOUT 100000
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#endif
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#include "nes_hw.h"
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#include "nes_verbs.h"
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#include "nes_context.h"
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#include <rdma/nes-abi.h>
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#include "nes_cm.h"
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#include "nes_mgt.h"
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extern int interrupt_mod_interval;
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extern int nes_if_count;
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extern int mpa_version;
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extern int disable_mpa_crc;
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extern unsigned int nes_drv_opt;
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extern unsigned int nes_debug_level;
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extern unsigned int wqm_quanta;
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extern struct list_head nes_adapter_list;
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extern atomic_t cm_connects;
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extern atomic_t cm_accepts;
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extern atomic_t cm_disconnects;
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extern atomic_t cm_closes;
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extern atomic_t cm_connecteds;
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extern atomic_t cm_connect_reqs;
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extern atomic_t cm_rejects;
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extern atomic_t mod_qp_timouts;
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extern atomic_t qps_created;
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extern atomic_t qps_destroyed;
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extern atomic_t sw_qps_destroyed;
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extern u32 mh_detected;
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extern u32 mh_pauses_sent;
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extern u32 cm_packets_sent;
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extern u32 cm_packets_bounced;
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extern u32 cm_packets_created;
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extern u32 cm_packets_received;
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extern u32 cm_packets_dropped;
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extern u32 cm_packets_retrans;
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extern atomic_t cm_listens_created;
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extern atomic_t cm_listens_destroyed;
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extern u32 cm_backlog_drops;
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extern atomic_t cm_loopbacks;
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extern atomic_t cm_nodes_created;
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extern atomic_t cm_nodes_destroyed;
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extern atomic_t cm_accel_dropped_pkts;
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extern atomic_t cm_resets_recvd;
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extern atomic_t pau_qps_created;
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extern atomic_t pau_qps_destroyed;
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extern u32 int_mod_timer_init;
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extern u32 int_mod_cq_depth_256;
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extern u32 int_mod_cq_depth_128;
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extern u32 int_mod_cq_depth_32;
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extern u32 int_mod_cq_depth_24;
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extern u32 int_mod_cq_depth_16;
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extern u32 int_mod_cq_depth_4;
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extern u32 int_mod_cq_depth_1;
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struct nes_device {
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struct nes_adapter *nesadapter;
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void __iomem *regs;
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void __iomem *index_reg;
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struct pci_dev *pcidev;
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struct net_device *netdev[NES_NIC_MAX_NICS];
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u64 link_status_interrupts;
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struct tasklet_struct dpc_tasklet;
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spinlock_t indexed_regs_lock;
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unsigned long csr_start;
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unsigned long doorbell_region;
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unsigned long doorbell_start;
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unsigned long mac_tx_errors;
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unsigned long mac_pause_frames_sent;
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unsigned long mac_pause_frames_received;
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unsigned long mac_rx_errors;
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unsigned long mac_rx_crc_errors;
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unsigned long mac_rx_symbol_err_frames;
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unsigned long mac_rx_jabber_frames;
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unsigned long mac_rx_oversized_frames;
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unsigned long mac_rx_short_frames;
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unsigned long port_rx_discards;
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unsigned long port_tx_discards;
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unsigned int mac_index;
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unsigned int nes_stack_start;
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/* Control Structures */
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void *cqp_vbase;
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dma_addr_t cqp_pbase;
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u32 cqp_mem_size;
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u8 ceq_index;
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u8 nic_ceq_index;
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struct nes_hw_cqp cqp;
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struct nes_hw_cq ccq;
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struct list_head cqp_avail_reqs;
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struct list_head cqp_pending_reqs;
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struct nes_cqp_request *nes_cqp_requests;
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u32 int_req;
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u32 int_stat;
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u32 timer_int_req;
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u32 timer_only_int_count;
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u32 intf_int_req;
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u32 last_mac_tx_pauses;
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u32 last_used_chunks_tx;
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struct list_head list;
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u16 base_doorbell_index;
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u16 currcq_count;
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u16 deepcq_count;
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u8 iw_status;
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u8 msi_enabled;
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u8 netdev_count;
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u8 napi_isr_ran;
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u8 disable_rx_flow_control;
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u8 disable_tx_flow_control;
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struct delayed_work work;
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u8 link_recheck;
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};
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/* Receive skb private area - must fit in skb->cb area */
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struct nes_rskb_cb {
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u64 busaddr;
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u32 maplen;
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u32 seqnum;
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u8 *data_start;
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struct nes_qp *nesqp;
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};
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static inline __le32 get_crc_value(struct nes_v4_quad *nes_quad)
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{
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u32 crc_value;
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crc_value = crc32c(~0, (void *)nes_quad, sizeof (struct nes_v4_quad));
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/*
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* With commit ef19454b ("[LIB] crc32c: Keep intermediate crc
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* state in cpu order"), behavior of crc32c changes on
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* big-endian platforms. Our algorithm expects the previous
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* behavior; otherwise we have RDMA connection establishment
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* issue on big-endian.
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*/
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return cpu_to_le32(crc_value);
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}
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static inline void
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set_wqe_64bit_value(__le32 *wqe_words, u32 index, u64 value)
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{
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wqe_words[index] = cpu_to_le32((u32) value);
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wqe_words[index + 1] = cpu_to_le32(upper_32_bits(value));
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}
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static inline void
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set_wqe_32bit_value(__le32 *wqe_words, u32 index, u32 value)
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{
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wqe_words[index] = cpu_to_le32(value);
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}
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static inline void
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nes_fill_init_cqp_wqe(struct nes_hw_cqp_wqe *cqp_wqe, struct nes_device *nesdev)
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{
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cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] = 0;
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cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = 0;
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cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
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cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
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cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX] = 0;
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cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_LEN_IDX] = 0;
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cqp_wqe->wqe_words[NES_CQP_STAG_WQE_LEN_LOW_IDX] = 0;
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cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_LOW_IDX] = 0;
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cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_HIGH_IDX] = 0;
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}
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static inline void
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nes_fill_init_qp_wqe(struct nes_hw_qp_wqe *wqe, struct nes_qp *nesqp, u32 head)
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{
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u32 value;
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value = ((u32)((unsigned long) nesqp)) | head;
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set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX,
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(u32)(upper_32_bits((unsigned long)(nesqp))));
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set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX, value);
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}
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/* Read from memory-mapped device */
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static inline u32 nes_read_indexed(struct nes_device *nesdev, u32 reg_index)
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{
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unsigned long flags;
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void __iomem *addr = nesdev->index_reg;
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u32 value;
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spin_lock_irqsave(&nesdev->indexed_regs_lock, flags);
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writel(reg_index, addr);
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value = readl((void __iomem *)addr + 4);
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spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags);
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return value;
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}
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static inline u32 nes_read32(const void __iomem *addr)
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{
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return readl(addr);
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}
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static inline u16 nes_read16(const void __iomem *addr)
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{
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return readw(addr);
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}
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static inline u8 nes_read8(const void __iomem *addr)
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{
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return readb(addr);
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}
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/* Write to memory-mapped device */
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static inline void nes_write_indexed(struct nes_device *nesdev, u32 reg_index, u32 val)
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{
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unsigned long flags;
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void __iomem *addr = nesdev->index_reg;
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spin_lock_irqsave(&nesdev->indexed_regs_lock, flags);
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writel(reg_index, addr);
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writel(val, (void __iomem *)addr + 4);
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spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags);
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}
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static inline void nes_write32(void __iomem *addr, u32 val)
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{
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writel(val, addr);
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}
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static inline void nes_write16(void __iomem *addr, u16 val)
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{
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writew(val, addr);
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}
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static inline void nes_write8(void __iomem *addr, u8 val)
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{
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writeb(val, addr);
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}
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enum nes_resource {
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NES_RESOURCE_MW = 1,
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NES_RESOURCE_FAST_MR,
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NES_RESOURCE_PHYS_MR,
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NES_RESOURCE_USER_MR,
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NES_RESOURCE_PD,
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NES_RESOURCE_QP,
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NES_RESOURCE_CQ,
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NES_RESOURCE_ARP
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};
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static inline int nes_alloc_resource(struct nes_adapter *nesadapter,
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unsigned long *resource_array, u32 max_resources,
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u32 *req_resource_num, u32 *next, enum nes_resource resource_type)
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{
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unsigned long flags;
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u32 resource_num;
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spin_lock_irqsave(&nesadapter->resource_lock, flags);
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resource_num = find_next_zero_bit(resource_array, max_resources, *next);
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if (resource_num >= max_resources) {
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resource_num = find_first_zero_bit(resource_array, max_resources);
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if (resource_num >= max_resources) {
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printk(KERN_ERR PFX "%s: No available resources [type=%u].\n", __func__, resource_type);
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spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
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return -EMFILE;
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}
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}
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set_bit(resource_num, resource_array);
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*next = resource_num+1;
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if (*next == max_resources) {
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*next = 0;
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}
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spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
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*req_resource_num = resource_num;
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return 0;
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}
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static inline int nes_is_resource_allocated(struct nes_adapter *nesadapter,
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unsigned long *resource_array, u32 resource_num)
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{
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unsigned long flags;
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int bit_is_set;
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spin_lock_irqsave(&nesadapter->resource_lock, flags);
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bit_is_set = test_bit(resource_num, resource_array);
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nes_debug(NES_DBG_HW, "resource_num %u is%s allocated.\n",
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resource_num, (bit_is_set ? "": " not"));
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spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
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return bit_is_set;
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}
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static inline void nes_free_resource(struct nes_adapter *nesadapter,
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unsigned long *resource_array, u32 resource_num)
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{
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unsigned long flags;
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spin_lock_irqsave(&nesadapter->resource_lock, flags);
|
|
clear_bit(resource_num, resource_array);
|
|
spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
|
|
}
|
|
|
|
static inline struct nes_vnic *to_nesvnic(struct ib_device *ibdev)
|
|
{
|
|
return container_of(ibdev, struct nes_ib_device, ibdev)->nesvnic;
|
|
}
|
|
|
|
static inline struct nes_pd *to_nespd(struct ib_pd *ibpd)
|
|
{
|
|
return container_of(ibpd, struct nes_pd, ibpd);
|
|
}
|
|
|
|
static inline struct nes_ucontext *to_nesucontext(struct ib_ucontext *ibucontext)
|
|
{
|
|
return container_of(ibucontext, struct nes_ucontext, ibucontext);
|
|
}
|
|
|
|
static inline struct nes_mr *to_nesmr(struct ib_mr *ibmr)
|
|
{
|
|
return container_of(ibmr, struct nes_mr, ibmr);
|
|
}
|
|
|
|
static inline struct nes_mr *to_nesmr_from_ibfmr(struct ib_fmr *ibfmr)
|
|
{
|
|
return container_of(ibfmr, struct nes_mr, ibfmr);
|
|
}
|
|
|
|
static inline struct nes_mr *to_nesmw(struct ib_mw *ibmw)
|
|
{
|
|
return container_of(ibmw, struct nes_mr, ibmw);
|
|
}
|
|
|
|
static inline struct nes_fmr *to_nesfmr(struct nes_mr *nesmr)
|
|
{
|
|
return container_of(nesmr, struct nes_fmr, nesmr);
|
|
}
|
|
|
|
static inline struct nes_cq *to_nescq(struct ib_cq *ibcq)
|
|
{
|
|
return container_of(ibcq, struct nes_cq, ibcq);
|
|
}
|
|
|
|
static inline struct nes_qp *to_nesqp(struct ib_qp *ibqp)
|
|
{
|
|
return container_of(ibqp, struct nes_qp, ibqp);
|
|
}
|
|
|
|
|
|
|
|
/* nes.c */
|
|
void nes_add_ref(struct ib_qp *);
|
|
void nes_rem_ref(struct ib_qp *);
|
|
struct ib_qp *nes_get_qp(struct ib_device *, int);
|
|
|
|
|
|
/* nes_hw.c */
|
|
struct nes_adapter *nes_init_adapter(struct nes_device *, u8);
|
|
void nes_nic_init_timer_defaults(struct nes_device *, u8);
|
|
void nes_destroy_adapter(struct nes_adapter *);
|
|
int nes_init_cqp(struct nes_device *);
|
|
int nes_init_phy(struct nes_device *);
|
|
int nes_init_nic_qp(struct nes_device *, struct net_device *);
|
|
void nes_destroy_nic_qp(struct nes_vnic *);
|
|
int nes_napi_isr(struct nes_device *);
|
|
void nes_dpc(unsigned long);
|
|
void nes_nic_ce_handler(struct nes_device *, struct nes_hw_nic_cq *);
|
|
void nes_iwarp_ce_handler(struct nes_device *, struct nes_hw_cq *);
|
|
int nes_destroy_cqp(struct nes_device *);
|
|
int nes_nic_cm_xmit(struct sk_buff *, struct net_device *);
|
|
void nes_recheck_link_status(struct work_struct *work);
|
|
void nes_terminate_timeout(struct timer_list *t);
|
|
|
|
/* nes_nic.c */
|
|
struct net_device *nes_netdev_init(struct nes_device *, void __iomem *);
|
|
void nes_netdev_destroy(struct net_device *);
|
|
int nes_nic_cm_xmit(struct sk_buff *, struct net_device *);
|
|
|
|
/* nes_cm.c */
|
|
void *nes_cm_create(struct net_device *);
|
|
int nes_cm_recv(struct sk_buff *, struct net_device *);
|
|
void nes_update_arp(unsigned char *, u32, u32, u16, u16);
|
|
void nes_manage_arp_cache(struct net_device *, unsigned char *, u32, u32);
|
|
void nes_sock_release(struct nes_qp *, unsigned long *);
|
|
void flush_wqes(struct nes_device *nesdev, struct nes_qp *, u32, u32);
|
|
int nes_manage_apbvt(struct nes_vnic *, u32, u32, u32);
|
|
int nes_cm_disconn(struct nes_qp *);
|
|
void nes_cm_disconn_worker(void *);
|
|
|
|
/* nes_verbs.c */
|
|
int nes_hw_modify_qp(struct nes_device *, struct nes_qp *, u32, u32, u32);
|
|
int nes_modify_qp(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *);
|
|
struct nes_ib_device *nes_init_ofa_device(struct net_device *);
|
|
void nes_port_ibevent(struct nes_vnic *nesvnic);
|
|
void nes_destroy_ofa_device(struct nes_ib_device *);
|
|
int nes_register_ofa_device(struct nes_ib_device *);
|
|
|
|
/* nes_util.c */
|
|
int nes_read_eeprom_values(struct nes_device *, struct nes_adapter *);
|
|
void nes_write_1G_phy_reg(struct nes_device *, u8, u8, u16);
|
|
void nes_read_1G_phy_reg(struct nes_device *, u8, u8, u16 *);
|
|
void nes_write_10G_phy_reg(struct nes_device *, u16, u8, u16, u16);
|
|
void nes_read_10G_phy_reg(struct nes_device *, u8, u8, u16);
|
|
struct nes_cqp_request *nes_get_cqp_request(struct nes_device *);
|
|
void nes_free_cqp_request(struct nes_device *nesdev,
|
|
struct nes_cqp_request *cqp_request);
|
|
void nes_put_cqp_request(struct nes_device *nesdev,
|
|
struct nes_cqp_request *cqp_request);
|
|
void nes_post_cqp_request(struct nes_device *, struct nes_cqp_request *);
|
|
int nes_arp_table(struct nes_device *, u32, u8 *, u32);
|
|
void nes_mh_fix(struct timer_list *t);
|
|
void nes_clc(struct timer_list *t);
|
|
void nes_dump_mem(unsigned int, void *, int);
|
|
u32 nes_crc32(u32, u32, u32, u32, u8 *, u32, u32, u32);
|
|
|
|
#endif /* __NES_H */
|