457 lines
8.8 KiB
C
Executable file
457 lines
8.8 KiB
C
Executable file
/*
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* Support for the Broadcom BCM3510 ATSC demodulator (1st generation Air2PC)
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*
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* Copyright (C) 2001-5, B2C2 inc.
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*
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* GPL/Linux driver written by Patrick Boettcher <patrick.boettcher@posteo.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __BCM3510_PRIV_H__
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#define __BCM3510_PRIV_H__
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#define PACKED __attribute__((packed))
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#undef err
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#define err(format, arg...) printk(KERN_ERR "bcm3510: " format "\n" , ## arg)
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#undef info
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#define info(format, arg...) printk(KERN_INFO "bcm3510: " format "\n" , ## arg)
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#undef warn
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#define warn(format, arg...) printk(KERN_WARNING "bcm3510: " format "\n" , ## arg)
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#define PANASONIC_FIRST_IF_BASE_IN_KHz 1407500
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#define BCM3510_SYMBOL_RATE 5381000
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typedef union {
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u8 raw;
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struct {
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u8 CTL :8;
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} TSTCTL_2e;
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u8 LDCERC_4e;
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u8 LDUERC_4f;
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u8 LD_BER0_65;
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u8 LD_BER1_66;
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u8 LD_BER2_67;
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u8 LD_BER3_68;
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struct {
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u8 RESET :1;
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u8 IDLE :1;
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u8 STOP :1;
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u8 HIRQ0 :1;
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u8 HIRQ1 :1;
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u8 na0 :1;
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u8 HABAV :1;
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u8 na1 :1;
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} HCTL1_a0;
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struct {
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u8 na0 :1;
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u8 IDLMSK :1;
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u8 STMSK :1;
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u8 I0MSK :1;
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u8 I1MSK :1;
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u8 na1 :1;
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u8 HABMSK :1;
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u8 na2 :1;
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} HCTLMSK_a1;
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struct {
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u8 RESET :1;
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u8 IDLE :1;
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u8 STOP :1;
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u8 RUN :1;
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u8 HABAV :1;
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u8 MEMAV :1;
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u8 ALDONE :1;
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u8 REIRQ :1;
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} APSTAT1_a2;
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struct {
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u8 RSTMSK :1;
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u8 IMSK :1;
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u8 SMSK :1;
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u8 RMSK :1;
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u8 HABMSK :1;
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u8 MAVMSK :1;
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u8 ALDMSK :1;
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u8 REMSK :1;
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} APMSK1_a3;
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u8 APSTAT2_a4;
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u8 APMSK2_a5;
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struct {
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u8 HABADR :7;
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u8 na :1;
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} HABADR_a6;
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u8 HABDATA_a7;
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struct {
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u8 HABR :1;
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u8 LDHABR :1;
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u8 APMSK :1;
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u8 HMSK :1;
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u8 LDMSK :1;
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u8 na :3;
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} HABSTAT_a8;
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u8 MADRH_a9;
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u8 MADRL_aa;
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u8 MDATA_ab;
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struct {
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#define JDEC_WAIT_AT_RAM 0x7
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#define JDEC_EEPROM_LOAD_WAIT 0x4
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u8 JDEC :3;
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u8 na :5;
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} JDEC_ca;
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struct {
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u8 REV :4;
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u8 LAYER :4;
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} REVID_e0;
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struct {
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u8 unk0 :1;
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u8 CNTCTL :1;
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u8 BITCNT :1;
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u8 unk1 :1;
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u8 RESYNC :1;
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u8 unk2 :3;
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} BERCTL_fa;
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struct {
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u8 CSEL0 :1;
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u8 CLKED0 :1;
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u8 CSEL1 :1;
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u8 CLKED1 :1;
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u8 CLKLEV :1;
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u8 SPIVAR :1;
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u8 na :2;
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} TUNSET_fc;
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struct {
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u8 CLK :1;
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u8 DATA :1;
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u8 CS0 :1;
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u8 CS1 :1;
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u8 AGCSEL :1;
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u8 na0 :1;
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u8 TUNSEL :1;
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u8 na1 :1;
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} TUNCTL_fd;
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u8 TUNSEL0_fe;
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u8 TUNSEL1_ff;
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} bcm3510_register_value;
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/* HAB commands */
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/* version */
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#define CMD_GET_VERSION_INFO 0x3D
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#define MSGID_GET_VERSION_INFO 0x15
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struct bcm3510_hab_cmd_get_version_info {
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u8 microcode_version;
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u8 script_version;
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u8 config_version;
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u8 demod_version;
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} PACKED;
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#define BCM3510_DEF_MICROCODE_VERSION 0x0E
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#define BCM3510_DEF_SCRIPT_VERSION 0x06
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#define BCM3510_DEF_CONFIG_VERSION 0x01
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#define BCM3510_DEF_DEMOD_VERSION 0xB1
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/* acquire */
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#define CMD_ACQUIRE 0x38
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#define MSGID_EXT_TUNER_ACQUIRE 0x0A
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struct bcm3510_hab_cmd_ext_acquire {
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struct {
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u8 MODE :4;
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u8 BW :1;
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u8 FA :1;
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u8 NTSCSWEEP :1;
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u8 OFFSET :1;
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} PACKED ACQUIRE0; /* control_byte */
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struct {
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u8 IF_FREQ :3;
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u8 zero0 :1;
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u8 SYM_RATE :3;
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u8 zero1 :1;
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} PACKED ACQUIRE1; /* sym_if */
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u8 IF_OFFSET0; /* IF_Offset_10hz */
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u8 IF_OFFSET1;
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u8 SYM_OFFSET0; /* SymbolRateOffset */
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u8 SYM_OFFSET1;
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u8 NTSC_OFFSET0; /* NTSC_Offset_10hz */
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u8 NTSC_OFFSET1;
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} PACKED;
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#define MSGID_INT_TUNER_ACQUIRE 0x0B
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struct bcm3510_hab_cmd_int_acquire {
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struct {
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u8 MODE :4;
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u8 BW :1;
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u8 FA :1;
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u8 NTSCSWEEP :1;
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u8 OFFSET :1;
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} PACKED ACQUIRE0; /* control_byte */
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struct {
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u8 IF_FREQ :3;
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u8 zero0 :1;
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u8 SYM_RATE :3;
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u8 zero1 :1;
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} PACKED ACQUIRE1; /* sym_if */
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u8 TUNER_FREQ0;
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u8 TUNER_FREQ1;
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u8 TUNER_FREQ2;
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u8 TUNER_FREQ3;
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u8 IF_OFFSET0; /* IF_Offset_10hz */
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u8 IF_OFFSET1;
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u8 SYM_OFFSET0; /* SymbolRateOffset */
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u8 SYM_OFFSET1;
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u8 NTSC_OFFSET0; /* NTSC_Offset_10hz */
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u8 NTSC_OFFSET1;
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} PACKED;
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/* modes */
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#define BCM3510_QAM16 = 0x01
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#define BCM3510_QAM32 = 0x02
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#define BCM3510_QAM64 = 0x03
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#define BCM3510_QAM128 = 0x04
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#define BCM3510_QAM256 = 0x05
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#define BCM3510_8VSB = 0x0B
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#define BCM3510_16VSB = 0x0D
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/* IF_FREQS */
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#define BCM3510_IF_TERRESTRIAL 0x0
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#define BCM3510_IF_CABLE 0x1
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#define BCM3510_IF_USE_CMD 0x7
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/* SYM_RATE */
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#define BCM3510_SR_8VSB 0x0 /* 5381119 s/sec */
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#define BCM3510_SR_256QAM 0x1 /* 5360537 s/sec */
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#define BCM3510_SR_16QAM 0x2 /* 5056971 s/sec */
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#define BCM3510_SR_MISC 0x3 /* 5000000 s/sec */
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#define BCM3510_SR_USE_CMD 0x7
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/* special symbol rate */
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#define CMD_SET_VALUE_NOT_LISTED 0x2d
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#define MSGID_SET_SYMBOL_RATE_NOT_LISTED 0x0c
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struct bcm3510_hab_cmd_set_sr_not_listed {
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u8 HOST_SYM_RATE0;
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u8 HOST_SYM_RATE1;
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u8 HOST_SYM_RATE2;
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u8 HOST_SYM_RATE3;
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} PACKED;
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/* special IF */
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#define MSGID_SET_IF_FREQ_NOT_LISTED 0x0d
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struct bcm3510_hab_cmd_set_if_freq_not_listed {
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u8 HOST_IF_FREQ0;
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u8 HOST_IF_FREQ1;
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u8 HOST_IF_FREQ2;
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u8 HOST_IF_FREQ3;
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} PACKED;
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/* auto reacquire */
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#define CMD_AUTO_PARAM 0x2a
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#define MSGID_AUTO_REACQUIRE 0x0e
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struct bcm3510_hab_cmd_auto_reacquire {
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u8 ACQ :1; /* on/off*/
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u8 unused :7;
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} PACKED;
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#define MSGID_SET_RF_AGC_SEL 0x12
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struct bcm3510_hab_cmd_set_agc {
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u8 LVL :1;
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u8 unused :6;
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u8 SEL :1;
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} PACKED;
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#define MSGID_SET_AUTO_INVERSION 0x14
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struct bcm3510_hab_cmd_auto_inversion {
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u8 AI :1;
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u8 unused :7;
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} PACKED;
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/* bert control */
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#define CMD_STATE_CONTROL 0x12
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#define MSGID_BERT_CONTROL 0x0e
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#define MSGID_BERT_SET 0xfa
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struct bcm3510_hab_cmd_bert_control {
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u8 BE :1;
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u8 unused :7;
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} PACKED;
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#define MSGID_TRI_STATE 0x2e
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struct bcm3510_hab_cmd_tri_state {
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u8 RE :1; /* a/d ram port pins */
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u8 PE :1; /* baud clock pin */
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u8 AC :1; /* a/d clock pin */
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u8 BE :1; /* baud clock pin */
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u8 unused :4;
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} PACKED;
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/* tune */
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#define CMD_TUNE 0x38
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#define MSGID_TUNE 0x16
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struct bcm3510_hab_cmd_tune_ctrl_data_pair {
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struct {
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#define BITS_8 0x07
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#define BITS_7 0x06
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#define BITS_6 0x05
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#define BITS_5 0x04
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#define BITS_4 0x03
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#define BITS_3 0x02
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#define BITS_2 0x01
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#define BITS_1 0x00
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u8 size :3;
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u8 unk :2;
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u8 clk_off :1;
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u8 cs0 :1;
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u8 cs1 :1;
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} PACKED ctrl;
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u8 data;
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} PACKED;
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struct bcm3510_hab_cmd_tune {
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u8 length;
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u8 clock_width;
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u8 misc;
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u8 TUNCTL_state;
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struct bcm3510_hab_cmd_tune_ctrl_data_pair ctl_dat[16];
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} PACKED;
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#define CMD_STATUS 0x38
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#define MSGID_STATUS1 0x08
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struct bcm3510_hab_cmd_status1 {
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struct {
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u8 EQ_MODE :4;
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u8 reserved :2;
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u8 QRE :1; /* if QSE and the spectrum is inversed */
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u8 QSE :1; /* automatic spectral inversion */
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} PACKED STATUS0;
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struct {
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u8 RECEIVER_LOCK :1;
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u8 FEC_LOCK :1;
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u8 OUT_PLL_LOCK :1;
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u8 reserved :5;
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} PACKED STATUS1;
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struct {
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u8 reserved :2;
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u8 BW :1;
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u8 NTE :1; /* NTSC filter sweep enabled */
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u8 AQI :1; /* currently acquiring */
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u8 FA :1; /* fast acquisition */
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u8 ARI :1; /* auto reacquire */
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u8 TI :1; /* programming the tuner */
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} PACKED STATUS2;
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u8 STATUS3;
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u8 SNR_EST0;
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u8 SNR_EST1;
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u8 TUNER_FREQ0;
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u8 TUNER_FREQ1;
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u8 TUNER_FREQ2;
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u8 TUNER_FREQ3;
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u8 SYM_RATE0;
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u8 SYM_RATE1;
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u8 SYM_RATE2;
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u8 SYM_RATE3;
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u8 SYM_OFFSET0;
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u8 SYM_OFFSET1;
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u8 SYM_ERROR0;
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u8 SYM_ERROR1;
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u8 IF_FREQ0;
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u8 IF_FREQ1;
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u8 IF_FREQ2;
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u8 IF_FREQ3;
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u8 IF_OFFSET0;
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u8 IF_OFFSET1;
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u8 IF_ERROR0;
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u8 IF_ERROR1;
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u8 NTSC_FILTER0;
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u8 NTSC_FILTER1;
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u8 NTSC_FILTER2;
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u8 NTSC_FILTER3;
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u8 NTSC_OFFSET0;
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u8 NTSC_OFFSET1;
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u8 NTSC_ERROR0;
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u8 NTSC_ERROR1;
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u8 INT_AGC_LEVEL0;
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u8 INT_AGC_LEVEL1;
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u8 EXT_AGC_LEVEL0;
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u8 EXT_AGC_LEVEL1;
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} PACKED;
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#define MSGID_STATUS2 0x14
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struct bcm3510_hab_cmd_status2 {
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struct {
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u8 EQ_MODE :4;
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u8 reserved :2;
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u8 QRE :1;
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u8 QSR :1;
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} PACKED STATUS0;
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struct {
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u8 RL :1;
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u8 FL :1;
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u8 OL :1;
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u8 reserved :5;
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} PACKED STATUS1;
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u8 SYMBOL_RATE0;
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u8 SYMBOL_RATE1;
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u8 SYMBOL_RATE2;
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u8 SYMBOL_RATE3;
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u8 LDCERC0;
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u8 LDCERC1;
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u8 LDCERC2;
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u8 LDCERC3;
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u8 LDUERC0;
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u8 LDUERC1;
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u8 LDUERC2;
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u8 LDUERC3;
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u8 LDBER0;
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u8 LDBER1;
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u8 LDBER2;
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u8 LDBER3;
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struct {
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u8 MODE_TYPE :4; /* acquire mode 0 */
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u8 reservd :4;
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} MODE_TYPE;
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u8 SNR_EST0;
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u8 SNR_EST1;
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u8 SIGNAL;
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} PACKED;
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#define CMD_SET_RF_BW_NOT_LISTED 0x3f
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#define MSGID_SET_RF_BW_NOT_LISTED 0x11
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/* TODO */
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#endif
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