651 lines
23 KiB
C
Executable file
651 lines
23 KiB
C
Executable file
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/*
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Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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* Neither the name of Trident Microsystems nor Hauppauge Computer Works
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nor the names of its contributors may be used to endorse or promote
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products derived from this software without specific prior written
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permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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DRXJ specific header file
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Authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen
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*/
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#ifndef __DRXJ_H__
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#define __DRXJ_H__
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/*-------------------------------------------------------------------------
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INCLUDES
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-------------------------------------------------------------------------*/
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#include "drx_driver.h"
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#include "drx_dap_fasi.h"
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/* Check DRX-J specific dap condition */
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/* Multi master mode and short addr format only will not work.
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RMW, CRC reset, broadcast and switching back to single master mode
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cannot be done with short addr only in multi master mode. */
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#if ((DRXDAP_SINGLE_MASTER == 0) && (DRXDAPFASI_LONG_ADDR_ALLOWED == 0))
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#error "Multi master mode and short addressing only is an illegal combination"
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*; /* Generate a fatal compiler error to make sure it stops here,
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this is necesarry because not all compilers stop after a #error. */
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#endif
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/*-------------------------------------------------------------------------
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TYPEDEFS
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-------------------------------------------------------------------------*/
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/*============================================================================*/
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/*============================================================================*/
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/*== code support ============================================================*/
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/*============================================================================*/
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/*============================================================================*/
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/*============================================================================*/
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/*============================================================================*/
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/*== SCU cmd if =============================================================*/
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/*============================================================================*/
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/*============================================================================*/
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struct drxjscu_cmd {
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u16 command;
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/*< Command number */
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u16 parameter_len;
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/*< Data length in byte */
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u16 result_len;
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/*< result length in byte */
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u16 *parameter;
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/*< General purpous param */
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u16 *result;
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/*< General purpous param */};
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/*============================================================================*/
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/*============================================================================*/
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/*== CTRL CFG related data structures ========================================*/
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/*============================================================================*/
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/*============================================================================*/
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/* extra intermediate lock state for VSB,QAM,NTSC */
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#define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1)
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/* OOB lock states */
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#define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */
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#define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */
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/* Intermediate powermodes for DRXJ */
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#define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8
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#define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9
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#define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10
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/* supstition for GPIO FNC mux */
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#define APP_O (0x0000)
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/*#define DRX_CTRL_BASE (0x0000)*/
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#define DRXJ_CTRL_CFG_BASE (0x1000)
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enum drxj_cfg_type {
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DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE,
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DRXJ_CFG_AGC_IF,
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DRXJ_CFG_AGC_INTERNAL,
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DRXJ_CFG_PRE_SAW,
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DRXJ_CFG_AFE_GAIN,
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DRXJ_CFG_SYMBOL_CLK_OFFSET,
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DRXJ_CFG_ACCUM_CR_RS_CW_ERR,
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DRXJ_CFG_FEC_MERS_SEQ_COUNT,
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DRXJ_CFG_OOB_MISC,
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DRXJ_CFG_SMART_ANT,
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DRXJ_CFG_OOB_PRE_SAW,
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DRXJ_CFG_VSB_MISC,
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DRXJ_CFG_RESET_PACKET_ERR,
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/* ATV (FM) */
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DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */
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DRXJ_CFG_ATV_MISC,
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DRXJ_CFG_ATV_EQU_COEF,
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DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */
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DRXJ_CFG_MPEG_OUTPUT_MISC,
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DRXJ_CFG_HW_CFG,
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DRXJ_CFG_OOB_LO_POW,
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DRXJ_CFG_MAX /* dummy, never to be used */};
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/*
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* /struct enum drxj_cfg_smart_ant_io * smart antenna i/o.
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*/
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enum drxj_cfg_smart_ant_io {
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DRXJ_SMT_ANT_OUTPUT = 0,
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DRXJ_SMT_ANT_INPUT
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};
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/*
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* /struct struct drxj_cfg_smart_ant * Set smart antenna.
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*/
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struct drxj_cfg_smart_ant {
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enum drxj_cfg_smart_ant_io io;
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u16 ctrl_data;
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};
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/*
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* /struct DRXJAGCSTATUS_t
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* AGC status information from the DRXJ-IQM-AF.
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*/
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struct drxj_agc_status {
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u16 IFAGC;
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u16 RFAGC;
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u16 digital_agc;
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};
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/* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */
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/*
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* /struct enum drxj_agc_ctrl_mode * Available AGCs modes in the DRXJ.
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*/
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enum drxj_agc_ctrl_mode {
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DRX_AGC_CTRL_AUTO = 0,
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DRX_AGC_CTRL_USER,
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DRX_AGC_CTRL_OFF};
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/*
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* /struct struct drxj_cfg_agc * Generic interface for all AGCs present on the DRXJ.
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*/
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struct drxj_cfg_agc {
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enum drx_standard standard; /* standard for which these settings apply */
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enum drxj_agc_ctrl_mode ctrl_mode; /* off, user, auto */
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u16 output_level; /* range dependent on AGC */
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u16 min_output_level; /* range dependent on AGC */
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u16 max_output_level; /* range dependent on AGC */
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u16 speed; /* range dependent on AGC */
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u16 top; /* rf-agc take over point */
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u16 cut_off_current; /* rf-agc is accelerated if output current
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is below cut-off current */};
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/* DRXJ_CFG_PRE_SAW */
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/*
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* /struct struct drxj_cfg_pre_saw * Interface to configure pre SAW sense.
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*/
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struct drxj_cfg_pre_saw {
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enum drx_standard standard; /* standard to which these settings apply */
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u16 reference; /* pre SAW reference value, range 0 .. 31 */
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bool use_pre_saw; /* true algorithms must use pre SAW sense */};
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/* DRXJ_CFG_AFE_GAIN */
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/*
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* /struct struct drxj_cfg_afe_gain * Interface to configure gain of AFE (LNA + PGA).
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*/
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struct drxj_cfg_afe_gain {
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enum drx_standard standard; /* standard to which these settings apply */
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u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */};
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/*
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* /struct drxjrs_errors
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* Available failure information in DRXJ_FEC_RS.
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*
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* Container for errors that are received in the most recently finished measurment period
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*
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*/
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struct drxjrs_errors {
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u16 nr_bit_errors;
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/*< no of pre RS bit errors */
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u16 nr_symbol_errors;
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/*< no of pre RS symbol errors */
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u16 nr_packet_errors;
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/*< no of pre RS packet errors */
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u16 nr_failures;
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/*< no of post RS failures to decode */
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u16 nr_snc_par_fail_count;
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/*< no of post RS bit erros */
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};
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/*
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* /struct struct drxj_cfg_vsb_misc * symbol error rate
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*/
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struct drxj_cfg_vsb_misc {
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u32 symb_error;
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/*< symbol error rate sps */};
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/*
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* /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate.
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*
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*/
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enum drxj_mpeg_start_width {
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DRXJ_MPEG_START_WIDTH_1CLKCYC,
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DRXJ_MPEG_START_WIDTH_8CLKCYC};
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/*
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* /enum enum drxj_mpeg_output_clock_rate * Mpeg output clock rate.
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*
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*/
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enum drxj_mpeg_output_clock_rate {
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DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO,
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DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K,
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DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K,
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DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K,
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DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K,
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DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K,
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DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K};
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/*
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* /struct DRXJCfgMisc_t
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* Change TEI bit of MPEG output
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* reverse MPEG output bit order
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* set MPEG output clock rate
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*/
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struct drxj_cfg_mpeg_output_misc {
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bool disable_tei_handling; /*< if true pass (not change) TEI bit */
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bool bit_reverse_mpeg_outout; /*< if true, parallel: msb on MD0; serial: lsb out first */
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enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate;
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/*< set MPEG output clock rate that overwirtes the derived one from symbol rate */
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enum drxj_mpeg_start_width mpeg_start_width; /*< set MPEG output start width */};
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/*
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* /enum enum drxj_xtal_freq * Supported external crystal reference frequency.
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*/
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enum drxj_xtal_freq {
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DRXJ_XTAL_FREQ_RSVD,
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DRXJ_XTAL_FREQ_27MHZ,
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DRXJ_XTAL_FREQ_20P25MHZ,
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DRXJ_XTAL_FREQ_4MHZ};
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/*
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* /enum enum drxj_xtal_freq * Supported external crystal reference frequency.
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*/
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enum drxji2c_speed {
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DRXJ_I2C_SPEED_400KBPS,
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DRXJ_I2C_SPEED_100KBPS};
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/*
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* /struct struct drxj_cfg_hw_cfg * Get hw configuration, such as crystal reference frequency, I2C speed, etc...
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*/
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struct drxj_cfg_hw_cfg {
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enum drxj_xtal_freq xtal_freq;
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/*< crystal reference frequency */
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enum drxji2c_speed i2c_speed;
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/*< 100 or 400 kbps */};
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/*
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* DRXJ_CFG_ATV_MISC
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*/
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struct drxj_cfg_atv_misc {
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s16 peak_filter; /* -8 .. 15 */
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u16 noise_filter; /* 0 .. 15 */};
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/*
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* struct drxj_cfg_oob_misc */
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#define DRXJ_OOB_STATE_RESET 0x0
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#define DRXJ_OOB_STATE_AGN_HUNT 0x1
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#define DRXJ_OOB_STATE_DGN_HUNT 0x2
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#define DRXJ_OOB_STATE_AGC_HUNT 0x3
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#define DRXJ_OOB_STATE_FRQ_HUNT 0x4
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#define DRXJ_OOB_STATE_PHA_HUNT 0x8
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#define DRXJ_OOB_STATE_TIM_HUNT 0x10
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#define DRXJ_OOB_STATE_EQU_HUNT 0x20
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#define DRXJ_OOB_STATE_EQT_HUNT 0x30
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#define DRXJ_OOB_STATE_SYNC 0x40
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struct drxj_cfg_oob_misc {
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struct drxj_agc_status agc;
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bool eq_lock;
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bool sym_timing_lock;
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bool phase_lock;
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bool freq_lock;
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bool dig_gain_lock;
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bool ana_gain_lock;
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u8 state;
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};
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/*
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* Index of in array of coef
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*/
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enum drxj_cfg_oob_lo_power {
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DRXJ_OOB_LO_POW_MINUS0DB = 0,
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DRXJ_OOB_LO_POW_MINUS5DB,
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DRXJ_OOB_LO_POW_MINUS10DB,
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DRXJ_OOB_LO_POW_MINUS15DB,
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DRXJ_OOB_LO_POW_MAX};
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/*
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* DRXJ_CFG_ATV_EQU_COEF
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*/
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struct drxj_cfg_atv_equ_coef {
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s16 coef0; /* -256 .. 255 */
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s16 coef1; /* -256 .. 255 */
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s16 coef2; /* -256 .. 255 */
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s16 coef3; /* -256 .. 255 */};
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/*
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* Index of in array of coef
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*/
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enum drxj_coef_array_index {
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DRXJ_COEF_IDX_MN = 0,
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DRXJ_COEF_IDX_FM,
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DRXJ_COEF_IDX_L,
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DRXJ_COEF_IDX_LP,
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DRXJ_COEF_IDX_BG,
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DRXJ_COEF_IDX_DK,
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DRXJ_COEF_IDX_I,
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DRXJ_COEF_IDX_MAX};
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/*
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* DRXJ_CFG_ATV_OUTPUT
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*/
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/*
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* /enum DRXJAttenuation_t
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* Attenuation setting for SIF AGC.
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*
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*/
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enum drxjsif_attenuation {
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DRXJ_SIF_ATTENUATION_0DB,
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DRXJ_SIF_ATTENUATION_3DB,
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DRXJ_SIF_ATTENUATION_6DB,
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DRXJ_SIF_ATTENUATION_9DB};
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/*
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* /struct struct drxj_cfg_atv_output * SIF attenuation setting.
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*
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*/
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struct drxj_cfg_atv_output {
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bool enable_cvbs_output; /* true= enabled */
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bool enable_sif_output; /* true= enabled */
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enum drxjsif_attenuation sif_attenuation;
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};
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/*
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DRXJ_CFG_ATV_AGC_STATUS (get only)
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*/
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/* TODO : AFE interface not yet finished, subject to change */
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struct drxj_cfg_atv_agc_status {
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u16 rf_agc_gain; /* 0 .. 877 uA */
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u16 if_agc_gain; /* 0 .. 877 uA */
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s16 video_agc_gain; /* -75 .. 1972 in 0.1 dB steps */
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s16 audio_agc_gain; /* -4 .. 1020 in 0.1 dB steps */
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u16 rf_agc_loop_gain; /* 0 .. 7 */
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u16 if_agc_loop_gain; /* 0 .. 7 */
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u16 video_agc_loop_gain; /* 0 .. 7 */};
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/*============================================================================*/
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/*============================================================================*/
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/*== CTRL related data structures ============================================*/
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/*============================================================================*/
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/*============================================================================*/
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/* NONE */
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/*============================================================================*/
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/*============================================================================*/
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/*========================================*/
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/*
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* /struct struct drxj_data * DRXJ specific attributes.
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*
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* Global data container for DRXJ specific data.
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*
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*/
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struct drxj_data {
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/* device capabilties (determined during drx_open()) */
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bool has_lna; /*< true if LNA (aka PGA) present */
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bool has_oob; /*< true if OOB supported */
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bool has_ntsc; /*< true if NTSC supported */
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bool has_btsc; /*< true if BTSC supported */
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bool has_smatx; /*< true if mat_tx is available */
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bool has_smarx; /*< true if mat_rx is available */
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bool has_gpio; /*< true if GPIO is available */
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bool has_irqn; /*< true if IRQN is available */
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/* A1/A2/A... */
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u8 mfx; /*< metal fix */
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/* tuner settings */
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bool mirror_freq_spect_oob;/*< tuner inversion (true = tuner mirrors the signal */
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/* standard/channel settings */
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enum drx_standard standard; /*< current standard information */
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enum drx_modulation constellation;
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/*< current constellation */
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s32 frequency; /*< center signal frequency in KHz */
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enum drx_bandwidth curr_bandwidth;
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/*< current channel bandwidth */
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enum drx_mirror mirror; /*< current channel mirror */
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/* signal quality information */
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u32 fec_bits_desired; /*< BER accounting period */
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u16 fec_vd_plen; /*< no of trellis symbols: VD SER measurement period */
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u16 qam_vd_prescale; /*< Viterbi Measurement Prescale */
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u16 qam_vd_period; /*< Viterbi Measurement period */
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u16 fec_rs_plen; /*< defines RS BER measurement period */
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u16 fec_rs_prescale; /*< ReedSolomon Measurement Prescale */
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u16 fec_rs_period; /*< ReedSolomon Measurement period */
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bool reset_pkt_err_acc; /*< Set a flag to reset accumulated packet error */
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u16 pkt_err_acc_start; /*< Set a flag to reset accumulated packet error */
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/* HI configuration */
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u16 hi_cfg_timing_div; /*< HI Configure() parameter 2 */
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u16 hi_cfg_bridge_delay; /*< HI Configure() parameter 3 */
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u16 hi_cfg_wake_up_key; /*< HI Configure() parameter 4 */
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u16 hi_cfg_ctrl; /*< HI Configure() parameter 5 */
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u16 hi_cfg_transmit; /*< HI Configure() parameter 6 */
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/* UIO configuration */
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enum drxuio_mode uio_sma_rx_mode;/*< current mode of SmaRx pin */
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enum drxuio_mode uio_sma_tx_mode;/*< current mode of SmaTx pin */
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enum drxuio_mode uio_gpio_mode; /*< current mode of ASEL pin */
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enum drxuio_mode uio_irqn_mode; /*< current mode of IRQN pin */
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/* IQM fs frequecy shift and inversion */
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u32 iqm_fs_rate_ofs; /*< frequency shifter setting after setchannel */
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bool pos_image; /*< Ture: positive image */
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/* IQM RC frequecy shift */
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u32 iqm_rc_rate_ofs; /*< frequency shifter setting after setchannel */
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/* ATV configuration */
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u32 atv_cfg_changed_flags; /*< flag: flags cfg changes */
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s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU0__A */
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s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU1__A */
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s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU2__A */
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s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /*< shadow of ATV_TOP_EQU3__A */
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bool phase_correction_bypass;/*< flag: true=bypass */
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s16 atv_top_vid_peak; /*< shadow of ATV_TOP_VID_PEAK__A */
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|
u16 atv_top_noise_th; /*< shadow of ATV_TOP_NOISE_TH__A */
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bool enable_cvbs_output; /*< flag CVBS ouput enable */
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|
bool enable_sif_output; /*< flag SIF ouput enable */
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enum drxjsif_attenuation sif_attenuation;
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|
/*< current SIF att setting */
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|
/* Agc configuration for QAM and VSB */
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struct drxj_cfg_agc qam_rf_agc_cfg; /*< qam RF AGC config */
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struct drxj_cfg_agc qam_if_agc_cfg; /*< qam IF AGC config */
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struct drxj_cfg_agc vsb_rf_agc_cfg; /*< vsb RF AGC config */
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struct drxj_cfg_agc vsb_if_agc_cfg; /*< vsb IF AGC config */
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|
|
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/* PGA gain configuration for QAM and VSB */
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u16 qam_pga_cfg; /*< qam PGA config */
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|
u16 vsb_pga_cfg; /*< vsb PGA config */
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|
|
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/* Pre SAW configuration for QAM and VSB */
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struct drxj_cfg_pre_saw qam_pre_saw_cfg;
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/*< qam pre SAW config */
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struct drxj_cfg_pre_saw vsb_pre_saw_cfg;
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/*< qam pre SAW config */
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|
|
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/* Version information */
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char v_text[2][12]; /*< allocated text versions */
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|
struct drx_version v_version[2]; /*< allocated versions structs */
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struct drx_version_list v_list_elements[2];
|
|
/*< allocated version list */
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|
|
|
/* smart antenna configuration */
|
|
bool smart_ant_inverted;
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|
|
|
/* Tracking filter setting for OOB */
|
|
u16 oob_trk_filter_cfg[8];
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|
bool oob_power_on;
|
|
|
|
/* MPEG static bitrate setting */
|
|
u32 mpeg_ts_static_bitrate; /*< bitrate static MPEG output */
|
|
bool disable_te_ihandling; /*< MPEG TS TEI handling */
|
|
bool bit_reverse_mpeg_outout;/*< MPEG output bit order */
|
|
enum drxj_mpeg_output_clock_rate mpeg_output_clock_rate;
|
|
/*< MPEG output clock rate */
|
|
enum drxj_mpeg_start_width mpeg_start_width;
|
|
/*< MPEG Start width */
|
|
|
|
/* Pre SAW & Agc configuration for ATV */
|
|
struct drxj_cfg_pre_saw atv_pre_saw_cfg;
|
|
/*< atv pre SAW config */
|
|
struct drxj_cfg_agc atv_rf_agc_cfg; /*< atv RF AGC config */
|
|
struct drxj_cfg_agc atv_if_agc_cfg; /*< atv IF AGC config */
|
|
u16 atv_pga_cfg; /*< atv pga config */
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|
|
|
u32 curr_symbol_rate;
|
|
|
|
/* pin-safe mode */
|
|
bool pdr_safe_mode; /*< PDR safe mode activated */
|
|
u16 pdr_safe_restore_val_gpio;
|
|
u16 pdr_safe_restore_val_v_sync;
|
|
u16 pdr_safe_restore_val_sma_rx;
|
|
u16 pdr_safe_restore_val_sma_tx;
|
|
|
|
/* OOB pre-saw value */
|
|
u16 oob_pre_saw;
|
|
enum drxj_cfg_oob_lo_power oob_lo_pow;
|
|
|
|
struct drx_aud_data aud_data;
|
|
/*< audio storage */};
|
|
|
|
/*-------------------------------------------------------------------------
|
|
Access MACROS
|
|
-------------------------------------------------------------------------*/
|
|
/*
|
|
* \brief Compilable references to attributes
|
|
* \param d pointer to demod instance
|
|
*
|
|
* Used as main reference to an attribute field.
|
|
* Can be used by both macro implementation and function implementation.
|
|
* These macros are defined to avoid duplication of code in macro and function
|
|
* definitions that handle access of demod common or extended attributes.
|
|
*
|
|
*/
|
|
|
|
#define DRXJ_ATTR_BTSC_DETECT(d) \
|
|
(((struct drxj_data *)(d)->my_ext_attr)->aud_data.btsc_detect)
|
|
|
|
/*-------------------------------------------------------------------------
|
|
DEFINES
|
|
-------------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* \def DRXJ_NTSC_CARRIER_FREQ_OFFSET
|
|
* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
|
|
*
|
|
* For NTSC standard.
|
|
* NTSC channels are listed by their picture carrier frequency (Fpc).
|
|
* The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input.
|
|
* In case the tuner module is not used the DRX-J requires that the tuner is
|
|
* tuned to the centre frequency of the channel:
|
|
*
|
|
* Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET
|
|
*
|
|
*/
|
|
#define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((s32)(1750))
|
|
|
|
/*
|
|
* \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET
|
|
* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
|
|
*
|
|
* For PAL/SECAM - BG standard. This define is needed in case the tuner module
|
|
* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc).
|
|
* The DRX-J requires that the tuner is tuned to:
|
|
* Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET
|
|
*
|
|
* In case the tuner module is used the drxdriver takes care of this.
|
|
* In case the tuner module is NOT used the application programmer must take
|
|
* care of this.
|
|
*
|
|
*/
|
|
#define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((s32)(2375))
|
|
|
|
/*
|
|
* \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET
|
|
* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
|
|
*
|
|
* For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module
|
|
* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc).
|
|
* The DRX-J requires that the tuner is tuned to:
|
|
* Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET
|
|
*
|
|
* In case the tuner module is used the drxdriver takes care of this.
|
|
* In case the tuner module is NOT used the application programmer must take
|
|
* care of this.
|
|
*
|
|
*/
|
|
#define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((s32)(2775))
|
|
|
|
/*
|
|
* \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET
|
|
* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
|
|
*
|
|
* For PAL/SECAM - LP standard. This define is needed in case the tuner module
|
|
* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc).
|
|
* The DRX-J requires that the tuner is tuned to:
|
|
* Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET
|
|
*
|
|
* In case the tuner module is used the drxdriver takes care of this.
|
|
* In case the tuner module is NOT used the application programmer must take
|
|
* care of this.
|
|
*/
|
|
#define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((s32)(-3255))
|
|
|
|
/*
|
|
* \def DRXJ_FM_CARRIER_FREQ_OFFSET
|
|
* \brief Offset from sound carrier to centre frequency in kHz, in RF domain
|
|
*
|
|
* For FM standard.
|
|
* FM channels are listed by their sound carrier frequency (Fsc).
|
|
* The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as
|
|
* input.
|
|
* In case the tuner module is not used the DRX-J requires that the tuner is
|
|
* tuned to the Ffm frequency of the channel.
|
|
*
|
|
* Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET
|
|
*
|
|
*/
|
|
#define DRXJ_FM_CARRIER_FREQ_OFFSET ((s32)(-3000))
|
|
|
|
/* Revision types -------------------------------------------------------*/
|
|
|
|
#define DRXJ_TYPE_ID (0x3946000DUL)
|
|
|
|
/* Macros ---------------------------------------------------------------*/
|
|
|
|
/* Convert OOB lock status to string */
|
|
#define DRXJ_STR_OOB_LOCKSTATUS(x) ( \
|
|
(x == DRX_NEVER_LOCK) ? "Never" : \
|
|
(x == DRX_NOT_LOCKED) ? "No" : \
|
|
(x == DRX_LOCKED) ? "Locked" : \
|
|
(x == DRX_LOCK_STATE_1) ? "AGC lock" : \
|
|
(x == DRX_LOCK_STATE_2) ? "sync lock" : \
|
|
"(Invalid)")
|
|
|
|
#endif /* __DRXJ_H__ */
|