178 lines
3.2 KiB
C
Executable file
178 lines
3.2 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __EDMA_DRIVER_H__
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#define __EDMA_DRIVER_H__
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#include "apusys_device.h"
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#include <linux/cdev.h>
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#define DEBUG
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#define EDMA_SUB_NUM 2
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#define EDMA_SUB_NAME_SIZE 20
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#define CMD_WAIT_TIME_MS (3 * 1000)
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struct edma_device;
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enum edma_sub_state {
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EDMA_UNPREPARE,
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EDMA_IDLE,
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EDMA_ACTIVE,
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EDMA_SLEEP,
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};
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enum edma_power_state {
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EDMA_POWER_OFF,
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EDMA_POWER_ON,
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};
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struct edma_sub {
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struct device *dev;
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struct apusys_device adev;
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u32 sub;
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struct edma_device *edma_device;
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spinlock_t reg_lock;
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void __iomem *base_addr;
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/* edma irq operation info */
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struct mutex cmd_mutex;
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wait_queue_head_t cmd_wait;
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bool is_cmd_done;
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enum edma_sub_state state;
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enum edma_power_state power_state;
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struct task_struct *enque_task;
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const void *plat_drv;
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u8 sub_name[EDMA_SUB_NAME_SIZE];
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uint32_t ip_time;
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unsigned int dbg_portID;
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};
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struct edma_device {
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struct device *dev;
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struct edma_sub *edma_sub[EDMA_SUB_NUM];
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struct timer_list power_timer;
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unsigned int edma_sub_num;
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/* notify enque thread */
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wait_queue_head_t req_wait;
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/* to check user list must have mutex protection */
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struct mutex power_mutex;
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enum edma_power_state power_state;
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struct work_struct power_off_work;
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dev_t edma_devt;
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struct cdev edma_chardev;
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struct dentry *debug_root;
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unsigned int dbgfs_reg_core;
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unsigned int dbg_cfg;
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};
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struct edma_user {
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pid_t open_pid;
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pid_t open_tgid;
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u32 id;
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struct device *dev;
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struct mutex data_mutex;
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bool running;
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bool flush;
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struct list_head enque_list;
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struct list_head deque_list;
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wait_queue_head_t deque_wait;
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};
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struct descriptor {
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u32 src_tile_channel;
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u32 src_tile_width;
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u32 src_tile_height;
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u32 src_channel_stride;
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u32 src_uv_channel_stride;
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u32 src_width_stride;
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u32 src_uv_width_stride;
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u32 dst_tile_channel;
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u32 dst_tile_width;
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u32 dst_channel_stride;
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u32 dst_uv_channel_stride;
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u32 dst_width_stride;
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u32 dst_uv_width_stride;
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u32 src_addr;
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u32 src_uv_addr;
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u32 dst_addr;
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u32 dst_uv_addr;
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u32 range_scale;
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u32 min_fp32;
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u32 param_a;
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u32 param_m;
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u32 cmprs_src_pxl;
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u32 cmprs_dst_pxl;
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u32 src_c_stride_pxl;
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u32 src_w_stride_pxl;
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u32 src_c_offset_m1;
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u32 src_w_offset_m1;
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u32 dst_c_stride_pxl;
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u32 dst_w_stride_pxl;
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u32 dst_c_offset_m1;
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u32 dst_w_offset_m1;
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u8 in_format;
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u8 out_format;
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u8 yuv2rgb_mat_bypass;
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u8 rgb2yuv_mat_bypass;
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u8 yuv2rgb_mat_select;
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u8 rgb2yuv_mat_select;
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u8 plane_num;
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u8 unpack_shift;
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u8 bit_num;
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};
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struct edma_request {
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u64 handle;
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u32 cmd;
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u32 sub;
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struct descriptor desp;
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u32 fill_value;
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u32 ext_reg_addr;
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u32 ext_count;
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u8 buf_iommu_en;
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u8 desp_iommu_en;
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s32 cmd_result;
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u32 cmd_status;
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};
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#define EDMA_EXT_MODE_SIZE 0x60
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enum edma_command_type {
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EDMA_PROC_NORMAL,
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EDMA_PROC_FILL,
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EDMA_PROC_NUMERICAL,
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EDMA_PROC_FORMAT,
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EDMA_PROC_COMPRESS,
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EDMA_PROC_DECOMPRESS,
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EDMA_PROC_RAW,
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EDMA_PROC_EXT_MODE,
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EDMA_PROC_MAX,
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};
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struct edma_ext {
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__u64 cmd_handle;
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__u32 count;
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__u32 reg_addr;
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__u32 fill_value;
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__u8 desp_iommu_en;
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} __attribute__ ((__packed__));
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//long edma_ioctl(struct file *flip, unsigned int cmd, unsigned long arg);
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int edma_initialize(struct edma_device *edma_device);
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#endif /* __EDMA_DRIVER_H__ */
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