267 lines
11 KiB
C
Executable file
267 lines
11 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*/
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#ifndef __CLDMA_REG_H__
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#define __CLDMA_REG_H__
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#include <mt-plat/sync_write.h>
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/* INFRA */
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#define INFRA_RST0_REG_PD (0x0150)/* rgu reset cldma reg */
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#define INFRA_RST1_REG_PD (0x0154)/* rgu clear cldma reset reg */
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#define CLDMA_PD_RST_MASK (1 << 2)
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#define INFRA_RST0_REG_AO (0x0140)
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#define INFRA_RST1_REG_AO (0x0144)
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#define CLDMA_AO_RST_MASK (1 << 6)
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#define INFRA_CLDMA_CTRL_REG (0x0C00)
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#define CLDMA_IP_BUSY_MASK (1 << 1)
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/* MD debug register */
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#define INFRA_AP2MD_DUMMY_REG (0x370)
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#define INFRA_AP2MD_DUMMY_BIT 0
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#define INFRA_MD2PERI_PROT_EN (0x250)
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#define INFRA_MD2PERI_PROT_RDY (0x258)
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#define INFRA_MD2PERI_PROT_SET (0x2A8)
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#define INFRA_MD2PERI_PROT_CLR (0x2AC)
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#define INFRA_MD2PERI_PROT_BIT 6
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#define INFRA_PERI2MD_PROT_EN (0x220)
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#define INFRA_PERI2MD_PROT_RDY (0x228)
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#define INFRA_PERI2MD_PROT_SET (0x2A0)
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#define INFRA_PERI2MD_PROT_CLR (0x2A4)
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#define INFRA_PERI2MD_PROT_BIT 7
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/* SRC CLK ENA */
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#define INFRA_AO_MD_SRCCLKENA (0xF0C)
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/*=====================CLDMA_AO_UL_CFG: 10014004-1001402C=====================*/
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/* The start address of first TGPD descriptor for power-down back-up. */
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#define CLDMA_AP_UL_START_ADDR_BK_0 (0x0004)
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#define CLDMA_AP_UL_START_ADDR_BK_1 (0x0008)
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#define CLDMA_AP_UL_START_ADDR_BK_2 (0x000C)
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#define CLDMA_AP_UL_START_ADDR_BK_3 (0x0010)
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#define CLDMA_AP_UL_START_ADDR_BK_4MSB (0x0014)
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/* The address of current processing TGPD descriptor for power-down back-up. */
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#define CLDMA_AP_UL_CURRENT_ADDR_BK_0 (0x0018)
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#define CLDMA_AP_UL_CURRENT_ADDR_BK_1 (0x001C)
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#define CLDMA_AP_UL_CURRENT_ADDR_BK_2 (0x0020)
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#define CLDMA_AP_UL_CURRENT_ADDR_BK_3 (0x0024)
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#define CLDMA_AP_UL_CURRENT_ADDR_BK_4MSB (0x0028)
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/*==================CLDMA_AO_DL_CFG:10014400-1001441C=========================*/
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/* Operation Configuration */
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#define CLDMA_AP_SO_CFG (0x0400)
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/* The start address of first RGPD descriptor */
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#define CLDMA_AP_SO_START_ADDR_0 (0x0404)
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/* The address of current processing RGPD descriptor. */
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#define CLDMA_AP_SO_CURRENT_ADDR_0 (0x0408)
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/* MSB 4 bits(35~32) of first RGPD */
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#define CLDMA_AP_SO_START_ADDR_4MSB (0x040C)
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/* MSB 4 bits(35~32) of current processing RGPD*/
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#define CLDMA_AP_SO_CURRENT_ADDR_4MSB (0x0410)
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/* SME OUT SBDMA operation status. */
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#define CLDMA_AP_SO_STATUS (0x0414)
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/* maximu MTU size */
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#define CLDMA_AP_DL_MTU_SIZE (0x0418)
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/*================CLDMA_AO_MISC: 10014800-1001480C===========================*/
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/* Level 2 Interrupt Mask Register (RX Part) */
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#define CLDMA_AP_L2RIMR0 (0x0800)
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/* Level 2 Interrupt Mask Clear Register (RX Part) */
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#define CLDMA_AP_L2RIMCR0 (0x0804)
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/* Level 2 Interrupt Mask Set Register (RX Part) */
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#define CLDMA_AP_L2RIMSR0 (0x0808)
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/*==============CLDMA_PD_UL_CFG: 1021B000-1021B070==========================*/
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/* The start address of first TGPD descriptor */
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#define CLDMA_AP_UL_START_ADDR_0 (0x0000)
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/* The start address of first TGPD descriptor */
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#define CLDMA_AP_UL_START_ADDR_1 (0x0004)
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/* The start address of first TGPD descriptor */
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#define CLDMA_AP_UL_START_ADDR_2 (0x0008)
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/* The start address of first TGPD descriptor */
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#define CLDMA_AP_UL_START_ADDR_3 (0x000C)
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#define CLDMA_AP_UL_START_ADDR_4MSB (0x0010)
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/* The address of current processing TGPD descriptor. */
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#define CLDMA_AP_UL_CURRENT_ADDR_0 (0x0014)
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/* The address of current processing TGPD descriptor. */
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#define CLDMA_AP_UL_CURRENT_ADDR_1 (0x0018)
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/* The address of current processing TGPD descriptor. */
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#define CLDMA_AP_UL_CURRENT_ADDR_2 (0x001C)
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/* The address of current processing TGPD descriptor. */
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#define CLDMA_AP_UL_CURRENT_ADDR_3 (0x0020)
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/* The last updated address[35:32] 4MSB BIT of TGPD */
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#define CLDMA_AP_UL_CURR_ADDR_4MSB (0x0024)
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/* UL SBDMA operation status. */
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#define CLDMA_AP_UL_STATUS (0x0028)
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/* UL START SBDMA command. */
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#define CLDMA_AP_UL_START_CMD (0x0030)
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/* UL RESUME SBDMA command. */
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#define CLDMA_AP_UL_RESUME_CMD (0x0034)
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/* UL STOP SBDMA command. */
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#define CLDMA_AP_UL_STOP_CMD (0x0038)
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#define CLDMA_AP_UL_ERROR (0x003C)/* ERROR */
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/* Operation Configuration */
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#define CLDMA_AP_UL_CFG (0x0040)
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/* The address of last updated TGPD descriptor. */
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#define CLDMA_AP_UL_LAST_UPDATE_ADDR_0 (0x0044)
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/* The address of last updated TGPD descriptor. */
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#define CLDMA_AP_UL_LAST_UPDATE_ADDR_1 (0x0048)
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/* The address of last updated TGPD descriptor. */
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#define CLDMA_AP_UL_LAST_UPDATE_ADDR_2 (0x004C)
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/* The address of last updated TGPD descriptor. */
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#define CLDMA_AP_UL_LAST_UPDATE_ADDR_3 (0x0050)
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/* The last updated address[35:32] 4MSB BIT of TGPD */
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#define CLDMA_AP_UL_LAST_UPDATE_ADDR_4MSB (0x0054)
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#define CLDMA_AP_UL_DEBUG_0 (0x0060)
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#define CLDMA_AP_UL_DEBUG_1 (0x0064)
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#define CLDMA_AP_UL_DEBUG_2 (0x0068)
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#define CLDMA_AP_UL_DEBUG_3 (0x006C)
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/*=================CLDMA_PD_DL_CFG:1021B400-1021B420==========================*/
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#define CLDMA_AP_SO_ERROR (0x0400)/* ERROR */
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/* SME OUT SBDMA START command. */
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#define CLDMA_AP_SO_START_CMD (0x0404)
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/* SO OUTDMA RESUME command. */
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#define CLDMA_AP_SO_RESUME_CMD (0x0408)
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/* SO OUTDMA STOP command. */
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#define CLDMA_AP_SO_STOP_CMD (0x040C)
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#define CLDMA_AP_DL_DEBUG_0 (0x0410)
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#define CLDMA_AP_DL_DEBUG_1 (0x0414)
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#define CLDMA_AP_DL_DEBUG_2 (0x0418)
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#define CLDMA_AP_DL_DEBUG_3 (0x041C)
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/*==================CLDMA_PD_AP_CFG: 1021B800-1021B8CC=======================*/
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/* Level 2 Interrupt Status and Acknowledgment Register (TX Part) */
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#define CLDMA_AP_L2TISAR0 (0x0800)
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/* Level 2 Interrupt Mask Register (TX Part) */
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#define CLDMA_AP_L2TIMR0 (0x0804)
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/* Level 2 Interrupt Mask Clear Register (TX Part) */
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#define CLDMA_AP_L2TIMCR0 (0x0808)
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/* Level 2 Interrupt Mask Set Register (TX Part) */
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#define CLDMA_AP_L2TIMSR0 (0x080C)
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/* Level 3 Interrupt Status and Acknowledgment Register (TX Part) */
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#define CLDMA_AP_L3TISAR0 (0x0810)
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/* Level 3 Interrupt Status and Acknowledgment Register (TX Part) */
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#define CLDMA_AP_L3TISAR1 (0x0814)
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/* Level 3 Interrupt Mask Register (TX Part) */
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#define CLDMA_AP_L3TIMR0 (0x0818)
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/* Level 3 Interrupt Mask Register (TX Part) */
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#define CLDMA_AP_L3TIMR1 (0x081C)
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/* Level 3 Interrupt Mask Clear Register (TX Part) */
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#define CLDMA_AP_L3TIMCR0 (0x0820)
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/* Level 3 Interrupt Mask Clear Register (TX Part) */
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#define CLDMA_AP_L3TIMCR1 (0x0824)
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/* Level 3 Interrupt Mask Set Register (TX Part) */
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#define CLDMA_AP_L3TIMSR0 (0x0828)
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/* Level 3 Interrupt Mask Set Register (TX Part) */
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#define CLDMA_AP_L3TIMSR1 (0x082C)
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/* Level 2 Interrupt Status and Acknowledgment Register (RX Part) */
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#define CLDMA_AP_L2RISAR0 (0x0830)
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/* Level 2 Interrupt Status and Acknowledgment Register (RX Part) */
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#define CLDMA_AP_L2RISAR1 (0x0834)
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/* Level 3 Interrupt Status and Acknowledgment Register (RX Part) */
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#define CLDMA_AP_L3RISAR0 (0x0838)
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/* Level 3 Interrupt Status and Acknowledgment Register (RX Part) */
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#define CLDMA_AP_L3RISAR1 (0x083C)
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/* Level 3 Interrupt Mask Register (RX Part) */
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#define CLDMA_AP_L3RIMR0 (0x0840)
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/* Level 3 Interrupt Mask Register (RX Part) */
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#define CLDMA_AP_L3RIMR1 (0x0844)
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/* Level 3 Interrupt Mask Clear Register (RX Part) */
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#define CLDMA_AP_L3RIMCR0 (0x0848)
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/* Level 3 Interrupt Mask Clear Register (RX Part) */
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#define CLDMA_AP_L3RIMCR1 (0x084C)
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/* Level 3 Interrupt MaskSet Register (RX Part) */
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#define CLDMA_AP_L3RIMSR0 (0x0850)
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/* Level 3 Interrupt Mask Set Register (RX Part) */
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#define CLDMA_AP_L3RIMSR1 (0x0854)
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#define CLDMA_AP_AXI_MI (0x0858)
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#define CLDMA_AP_CLDMA_IP_BUSY (0x0860) /* CLDMA IP busy */
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/*Hardware DVFS control Register*/
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#define CLDMA_AP_HW_DVFS_CTRL (0x0864)
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#define CLDMA_AP_QOS (0x0868)
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#define CLDMA_AP_DMA_ERR (0x0870) /* exception status */
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#define CLDMA_AP_DMA_ERR_MASK (0x0874) /* exception mask */
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#define CLDMA_AP_DEBUG0 (0x0878)
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/*assistant macros*/
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#define CLDMA_AP_TQSAR(i) (CLDMA_AP_UL_START_ADDR_0 + (4 * (i)))
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#define CLDMA_AP_TQCPR(i) (CLDMA_AP_UL_CURRENT_ADDR_0 + (4 * (i)))
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#define CLDMA_AP_RQSAR(i) (CLDMA_AP_SO_START_ADDR_0 + (4 * (i)))
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#define CLDMA_AP_RQCPR(i) (CLDMA_AP_SO_CURRENT_ADDR_0 + (4 * (i)))
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#define CLDMA_AP_TQSABAK(i) (CLDMA_AP_UL_START_ADDR_BK_0 + (4 * (i)))
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#define CLDMA_AP_TQCPBAK(i) (CLDMA_AP_UL_CURRENT_ADDR_BK_0 + (4 * (i)))
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#define cldma_write32(b, a, v) mt_reg_sync_writel(v, (b)+(a))
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#define cldma_write16(b, a, v) mt_reg_sync_writew(v, (b)+(a))
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#define cldma_write8(b, a, v) mt_reg_sync_writeb(v, (b)+(a))
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#define cldma_read32(b, a) ioread32((void __iomem *)((b)+(a)))
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#define cldma_read16(b, a) ioread16((void __iomem *)((b)+(a)))
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#define cldma_read8(b, a) ioread8((void __iomem *)((b)+(a)))
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/*bitmap*/
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#define CLDMA_BM_INT_ALL 0xFFFFFFFF
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/* L2 interrupt */
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/* error occurred on the specified queue, check L3 for detail */
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#define CLDMA_TX_INT_ERROR 0x00000F00
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/* when there is no GPD to be transmitted on the specified queue */
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#define CLDMA_TX_INT_QUEUE_EMPTY 0x000000F0
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#define CLDMA_TX_QE_OFFSET 4
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/* when the transmission if the GPD on the specified queue is done */
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#define CLDMA_TX_INT_DONE 0x0000000F
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/* error occurred on the specified queue, check L3 for detail */
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#define CLDMA_RX_INT_ERROR 0x00000004
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/* when there is no GPD to be transmitted on the specified queue */
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#define CLDMA_RX_INT_QUEUE_EMPTY 0x00000002
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#define CLDMA_RX_QE_OFFSET 1
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/* when the transmission if the GPD on the specified queue is done */
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#define CLDMA_RX_INT_DONE 0x00000001
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#define CLDMA_BM_ALL_QUEUE 0x0F /* all queues */
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static inline void cldma_reg_set_4msb_val(
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void *base, unsigned int reg_4msb_offset, int idx, dma_addr_t addr)
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{
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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unsigned int val = 0;
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val = cldma_read32(base, reg_4msb_offset);
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val &= ~(0xF << (idx * 4)); /*clear 0xF << i*4 bit */
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val |= (((addr >> 32) & 0xF) << (idx * 4)); /*set 4msb bit*/
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cldma_write32(base, reg_4msb_offset, val);
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#endif
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}
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static inline unsigned int cldma_reg_get_4msb_val(
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void *base, unsigned int reg_4msb_offset, int idx)
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{
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unsigned int val = 0;
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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val = cldma_read32(base, reg_4msb_offset);
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val &= (0xF << (idx * 4)); /*clear no need bit, keep 0xF << i*4 bit */
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val >>= (idx * 4); /* get 4msb bit*/
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#endif
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return val;
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}
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static inline void cldma_reg_set_tx_start_addr(
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void *base, int idx, dma_addr_t addr)
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{
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cldma_write32(base, CLDMA_AP_TQSAR(idx), (u32)addr);
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cldma_reg_set_4msb_val(base, CLDMA_AP_UL_START_ADDR_4MSB, idx, addr);
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}
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static inline void cldma_reg_set_tx_start_addr_bk(
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void *base, int idx, dma_addr_t addr)
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{
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/*Set start bak address in power on domain*/
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cldma_write32(base, CLDMA_AP_TQSABAK(idx), (u32)addr);
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cldma_reg_set_4msb_val(base, CLDMA_AP_UL_START_ADDR_BK_4MSB, idx, addr);
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}
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static inline void cldma_reg_set_rx_start_addr(
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void *base, int idx, dma_addr_t addr)
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{
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cldma_write32(base, CLDMA_AP_RQSAR(idx), (u32)addr);
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cldma_reg_set_4msb_val(base, CLDMA_AP_SO_START_ADDR_4MSB, idx, addr);
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}
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#endif /* __CLDMA_REG_H__ */
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