339 lines
6.9 KiB
C
Executable file
339 lines
6.9 KiB
C
Executable file
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Sagy Shih <sagy.shih@mediatek.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/printk.h>
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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#include <mt_emi.h>
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#include "emi_ctrl_v1.h"
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static void __iomem *CEN_EMI_BASE;
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static void __iomem *CHN_EMI_BASE[MAX_CH];
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#ifdef ENABLE_EMI_DEBUG_API
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static void __iomem *EMI_DBG_BASE[MAX_DBG_NR];
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#endif
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static void __iomem *EMI_MPU_BASE;
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static struct emi_info_t emi_info;
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static unsigned int emi_dcm;
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static int emi_probe(struct platform_device *pdev);
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static int ddr_info_show(struct seq_file *m, void *v)
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{
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unsigned char buf[128];
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ssize_t ret;
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unsigned int density, rank, ddr_info;
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ret = 0;
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for (rank = 0, density = 0; rank < get_rk_num(); rank++)
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density += get_rank_size(rank);
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density *= 128;
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ddr_info = ((density >> 2) & 0xF00) | get_dram_mr(5);
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ret += snprintf(buf + ret, sizeof(buf) - ret,
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"ddr_info: 0x%x\n", ddr_info);
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ret += snprintf(buf + ret, sizeof(buf) - ret,
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"DRAM density: %d MB\n", density);
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ret += snprintf(buf + ret, sizeof(buf) - ret,
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"vendor ID: 0x%x\n", get_dram_mr(5));
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seq_write(m, buf, ret);
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return 0;
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}
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static int ddr_info_open(struct inode *inode, struct file *file)
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{
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return single_open(file, ddr_info_show, NULL);
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}
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static const struct file_operations ddr_info_proc_fops = {
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.open = ddr_info_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int emi_remove(struct platform_device *dev)
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{
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return 0;
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}
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#ifdef CONFIG_OF
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static const struct of_device_id emi_of_ids[] = {
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{.compatible = "mediatek,emi",},
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{}
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};
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#endif
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#ifdef CONFIG_PM
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static int emi_suspend_noirq(struct device *dev)
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{
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/* pr_info("[EMI] suspend\n"); */
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#if ENABLE_ELM
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suspend_elm();
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#endif
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return 0;
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}
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static int emi_resume_noirq(struct device *dev)
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{
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/* pr_info("[EMI] resume\n"); */
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#if ENABLE_ELM
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resume_elm();
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#endif
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#ifdef DECS_ON_SSPM
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resume_decs(CEN_EMI_BASE);
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#endif
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return 0;
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}
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static const struct dev_pm_ops emi_pm_ops = {
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.suspend_noirq = emi_suspend_noirq,
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.resume_noirq = emi_resume_noirq,
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};
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#define EMI_PM_OPS (&emi_pm_ops)
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#else
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#define EMI_PM_OPS NULL
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#endif
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static struct platform_driver emi_ctrl = {
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.probe = emi_probe,
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.remove = emi_remove,
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.driver = {
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.name = "emi_ctrl",
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.owner = THIS_MODULE,
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.pm = EMI_PM_OPS,
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#ifdef CONFIG_OF
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.of_match_table = emi_of_ids,
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#endif
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},
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};
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__weak void plat_debug_api_init(void)
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{
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}
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static int emi_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct proc_dir_entry *proc_entry;
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int i;
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pr_info("[EMI] module probe.\n");
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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CEN_EMI_BASE = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(CEN_EMI_BASE)) {
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pr_err("[EMI] unable to map CEN_EMI_BASE\n");
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return -EINVAL;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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EMI_MPU_BASE = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(EMI_MPU_BASE)) {
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pr_err("[EMI] unable to map EMI_MPU_BASE\n");
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return -EINVAL;
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}
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for (i = 0; i < MAX_CH; i++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + i);
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CHN_EMI_BASE[i] = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(CHN_EMI_BASE[i])) {
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pr_err("[EMI] unable to map CH%d_EMI_BASE\n", i);
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return -EINVAL;
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}
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}
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#ifdef ENABLE_EMI_DEBUG_API
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for (i = 0; i < MAX_DBG_NR; i++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM,
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2 + MAX_CH + i);
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EMI_DBG_BASE[i] = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(EMI_DBG_BASE[i])) {
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pr_debug("[EMI] unable to map dbg\n");
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return -EINVAL;
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}
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}
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of_property_read_u32(pdev->dev.of_node,
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"emi_dcm", &emi_dcm);
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plat_debug_api_init();
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#endif
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pr_info("[EMI] get CEN_EMI_BASE @ %p\n", mt_cen_emi_base_get());
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pr_info("[EMI] get EMI_MPU_BASE @ %p\n", mt_emi_mpu_base_get());
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for (i = 0; i < MAX_CH; i++)
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pr_info("[EMI] get CH%d_EMI_BASE @ %p\n",
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i, mt_chn_emi_base_get(i));
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proc_entry = proc_create("ddr_info", 0444, NULL, &ddr_info_proc_fops);
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#if ENABLE_BWL
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bwl_init(&emi_ctrl);
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#endif
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#if ENABLE_MPU
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mpu_init(&emi_ctrl, pdev);
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#endif
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#if ENABLE_ELM
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elm_init(&emi_ctrl, pdev);
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#endif
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#if ENABLE_MBW
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mbw_init(&emi_ctrl);
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#endif
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return 0;
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}
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/*
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* emi_ctrl_init: module init function.
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*/
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static int __init emi_ctrl_init(void)
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{
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int ret;
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int i;
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struct device_node *node;
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/* register EMI ctrl interface */
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ret = platform_driver_register(&emi_ctrl);
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if (ret)
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pr_err("[EMI/BWL] fail to register emi_ctrl driver\n");
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/* get EMI info from boot tags */
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node = of_find_compatible_node(NULL, NULL, "mediatek,emi");
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if (node) {
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ret = of_property_read_u32(node,
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"emi_info,dram_type", &(emi_info.dram_type));
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if (ret)
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pr_err("[EMI] fail to get dram_type\n");
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ret = of_property_read_u32(node,
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"emi_info,ch_num", &(emi_info.ch_num));
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if (ret)
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pr_err("[EMI] fail to get ch_num\n");
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ret = of_property_read_u32(node,
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"emi_info,rk_num", &(emi_info.rk_num));
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if (ret)
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pr_err("[EMI] fail to get rk_num\n");
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ret = of_property_read_u32_array(node, "emi_info,rank_size",
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emi_info.rank_size, MAX_RK);
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if (ret)
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pr_err("[EMI] fail to get rank_size\n");
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}
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pr_info("[EMI] dram_type(%d)\n", get_dram_type());
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pr_info("[EMI] mr5(0x%x)\n", get_dram_mr(5));
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pr_info("[EMI] ch_num(%d)\n", get_ch_num());
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pr_info("[EMI] rk_num(%d)\n", get_rk_num());
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for (i = 0; i < get_rk_num(); i++)
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pr_info("[EMI] rank%d_size(0x%x)", i, get_rank_size(i));
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return 0;
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}
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/*
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* emi_ctrl_exit: module exit function.
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*/
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static void __exit emi_ctrl_exit(void)
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{
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}
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postcore_initcall(emi_ctrl_init);
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module_exit(emi_ctrl_exit);
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unsigned int get_dram_type(void)
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{
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return (emi_info.dram_type & 0xF);
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}
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unsigned int get_dram_mr(unsigned int index)
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{
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switch (index) {
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case 5:
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return ((emi_info.dram_type >> 24) & 0xFF);
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default:
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return 0;
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}
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}
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unsigned int get_ch_num(void)
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{
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return emi_info.ch_num;
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}
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unsigned int get_rk_num(void)
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{
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return emi_info.rk_num;
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}
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unsigned int get_rank_size(unsigned int rank_index)
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{
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if ((rank_index < emi_info.rk_num) && (rank_index < MAX_RK))
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return emi_info.rank_size[rank_index];
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return 0;
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}
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void __iomem *mt_cen_emi_base_get(void)
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{
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return CEN_EMI_BASE;
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}
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EXPORT_SYMBOL(mt_cen_emi_base_get);
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/* for legacy use */
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void __iomem *mt_emi_base_get(void)
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{
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return mt_cen_emi_base_get();
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}
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EXPORT_SYMBOL(mt_emi_base_get);
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void __iomem *mt_chn_emi_base_get(unsigned int channel_index)
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{
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if (channel_index < MAX_CH)
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return CHN_EMI_BASE[channel_index];
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return NULL;
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}
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EXPORT_SYMBOL(mt_chn_emi_base_get);
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#ifdef ENABLE_EMI_DEBUG_API
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void __iomem *mt_emi_dbg_base_get(unsigned int index)
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{
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if (index < MAX_DBG_NR)
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return EMI_DBG_BASE[index];
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return NULL;
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}
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EXPORT_SYMBOL(mt_emi_dbg_base_get);
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#endif
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void __iomem *mt_emi_mpu_base_get(void)
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{
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return EMI_MPU_BASE;
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}
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EXPORT_SYMBOL(mt_emi_mpu_base_get);
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unsigned int mt_emi_dcm_config(void)
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{
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return emi_dcm;
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}
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EXPORT_SYMBOL(mt_emi_dcm_config);
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