200 lines
5.4 KiB
C
Executable file
200 lines
5.4 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _MTK_SMI_H_
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#define _MTK_SMI_H_
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#define MTK_SMI_MAJOR_NUMBER 190
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#define MTK_IOW(num, dtype) _IOW('O', num, dtype)
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#define MTK_IOR(num, dtype) _IOR('O', num, dtype)
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#define MTK_IOWR(num, dtype) _IOWR('O', num, dtype)
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#define MTK_IO(num) _IO('O', num)
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/* -------------------------------------------------------------------------- */
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#define MTK_CONFIG_MM_MAU MTK_IOW(10, unsigned long)
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struct MTK_MAU_CONFIG {
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int larb; /* 0~4: the larb you want to monitor */
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int entry; /* 0~2: the mau entry to use */
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unsigned int port_msk; /* port mask to be monitored */
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int virt; /* 1: monitor va (this port is using m4u); */
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/* 0: monitor pa (this port is not using m4u) */
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int monitor_read; /* monitor read transaction 1-enable, 0-disable */
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int monitor_write; /* monitor write transaction 1-enable, 0-disable */
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unsigned int start; /* start address to monitor */
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unsigned int end; /* end address to monitor */
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};
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int mau_config(struct MTK_MAU_CONFIG *pMauConf);
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int mau_dump_status(int larb);
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/* ------------------------------------------------------------------------- */
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enum MTK_SMI_BWC_SCEN {
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SMI_BWC_SCEN_NORMAL,
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SMI_BWC_SCEN_VR,
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SMI_BWC_SCEN_SWDEC_VP,
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SMI_BWC_SCEN_VP,
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SMI_BWC_SCEN_VP_4KOSD,
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SMI_BWC_SCEN_VP_HIGH_FPS,
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SMI_BWC_SCEN_VP_HIGH_RESOLUTION,
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SMI_BWC_SCEN_VR_SLOW,
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SMI_BWC_SCEN_MM_GPU,
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SMI_BWC_SCEN_WFD,
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SMI_BWC_SCEN_VENC,
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SMI_BWC_SCEN_ICFP,
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SMI_BWC_SCEN_UI_IDLE,
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SMI_BWC_SCEN_VSS,
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SMI_BWC_SCEN_FORCE_MMDVFS,
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SMI_BWC_SCEN_HDMI,
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SMI_BWC_SCEN_HDMI4K,
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SMI_BWC_SCEN_VPMJC,
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SMI_BWC_SCEN_N3D,
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SMI_BWC_SCEN_CNT
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};
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/* MMDVFS */
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enum mmdvfs_voltage_enum {
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MMDVFS_VOLTAGE_DEFAULT,
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MMDVFS_VOLTAGE_0 = MMDVFS_VOLTAGE_DEFAULT,
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MMDVFS_VOLTAGE_LOW = MMDVFS_VOLTAGE_0,
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MMDVFS_VOLTAGE_1,
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MMDVFS_VOLTAGE_HIGH = MMDVFS_VOLTAGE_1,
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MMDVFS_VOLTAGE_DEFAULT_STEP,
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MMDVFS_VOLTAGE_COUNT
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};
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struct MTK_SMI_BWC_CONFIG {
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enum MTK_SMI_BWC_SCEN scenario;
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int b_on_off; /* 0 : exit this scenario , 1 : enter this scenario */
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};
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struct MTK_SMI_BWC_STATE {
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unsigned int *hwc_max_pixel;
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};
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struct MTK_SMI_BWC_REGISTER_SET {
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unsigned int address;
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unsigned int value;
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};
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struct MTK_SMI_BWC_REGISTER_GET {
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unsigned int address;
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unsigned int *return_address;
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};
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#define MMDVFS_CAMERA_MODE_FLAG_DEFAULT 1
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#define MMDVFS_CAMERA_MODE_FLAG_PIP (1 << 1)
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#define MMDVFS_CAMERA_MODE_FLAG_VFB (1 << 2)
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#define MMDVFS_CAMERA_MODE_FLAG_EIS_2_0 (1 << 3)
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#define MMDVFS_CAMERA_MODE_FLAG_IVHDR (1 << 4)
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#define MMDVFS_CAMERA_MODE_FLAG_STEREO (1 << 5)
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struct MTK_MMDVFS_CMD {
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unsigned int type;
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enum MTK_SMI_BWC_SCEN scen;
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unsigned int sensor_size;
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unsigned int sensor_fps;
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unsigned int camera_mode;
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unsigned int venc_size;
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unsigned int ret;
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};
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#define MTK_MMDVFS_CMD_TYPE_SET 0
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#define MTK_MMDVFS_CMD_TYPE_QUERY 1
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enum MTK_SMI_BWC_INFO_ID {
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SMI_BWC_INFO_CON_PROFILE = 0,
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SMI_BWC_INFO_SENSOR_SIZE,
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SMI_BWC_INFO_VIDEO_RECORD_SIZE,
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SMI_BWC_INFO_DISP_SIZE,
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SMI_BWC_INFO_TV_OUT_SIZE,
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SMI_BWC_INFO_FPS,
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SMI_BWC_INFO_VIDEO_ENCODE_CODEC,
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SMI_BWC_INFO_VIDEO_DECODE_CODEC,
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SMI_BWC_INFO_HW_OVL_LIMIT,
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SMI_BWC_INFO_CNT
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};
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struct MTK_SMI_BWC_INFO_SET {
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int property;
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int value1;
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int value2;
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};
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struct MTK_SMI_BWC_MM_INFO {
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unsigned int flag; /* Reserved */
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int concurrent_profile;
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int sensor_size[2];
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int video_record_size[2];
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int display_size[2];
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int tv_out_size[2];
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int fps;
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int video_encode_codec;
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int video_decode_codec;
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int hw_ovl_limit;
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};
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#define MTK_IOC_SPC_CONFIG MTK_IOW(20, unsigned long)
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#define MTK_IOC_SPC_DUMP_REG MTK_IOW(21, unsigned long)
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#define MTK_IOC_SPC_DUMP_STA MTK_IOW(22, unsigned long)
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#define MTK_IOC_SPC_CMD MTK_IOW(23, unsigned long)
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#define MTK_IOC_SMI_BWC_CONFIG MTK_IOW(24, struct MTK_SMI_BWC_CONFIG)
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#define MTK_IOC_SMI_BWC_STATE MTK_IOWR(25, struct MTK_SMI_BWC_STATE)
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#define MTK_IOC_SMI_BWC_REGISTER_SET \
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MTK_IOWR(26, struct MTK_SMI_BWC_REGISTER_SET)
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#define MTK_IOC_SMI_BWC_REGISTER_GET \
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MTK_IOWR(27, struct MTK_SMI_BWC_REGISTER_GET)
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/* For BWC.MM property setting */
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#define MTK_IOC_SMI_BWC_INFO_SET MTK_IOWR(28, struct MTK_SMI_BWC_INFO_SET)
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/* For BWC.MM property get */
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#define MTK_IOC_SMI_BWC_INFO_GET MTK_IOWR(29, struct MTK_SMI_BWC_MM_INFO)
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/* GMP end */
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#define MTK_IOC_SMI_DUMP_LARB MTK_IOWR(66, unsigned int)
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#define MTK_IOC_SMI_DUMP_COMMON MTK_IOWR(67, unsigned int)
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#define MTK_IOC_MMDVFS_CMD MTK_IOW(88, struct MTK_MMDVFS_CMD)
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enum SPC_PROT_T {
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SPC_PROT_NO_PROT = 0,
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SPC_PROT_SEC_RW_ONLY,
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SPC_PROT_SEC_RW_NONSEC_R,
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SPC_PROT_NO_ACCESS,
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};
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struct MTK_SPC_CONFIG {
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enum SPC_PROT_T domain_0_prot;
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enum SPC_PROT_T domain_1_prot;
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enum SPC_PROT_T domain_2_prot;
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enum SPC_PROT_T domain_3_prot;
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unsigned int start; /* start address to monitor */
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unsigned int end; /* end address to monitor */
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};
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void spc_config(struct MTK_SPC_CONFIG *pCfg);
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unsigned int spc_status_check(void);
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unsigned int spc_dump_reg(void);
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unsigned int spc_register_isr(void *dev);
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unsigned int spc_clear_irq(void);
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int spc_test(int code);
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int MTK_SPC_Init(void *dev);
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#define MMDVFS_ENABLE_DEFAULT_STEP_QUERY
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#define MMDVFS_MMCLOCK_NOTIFICATION
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/* MMDVFS kernel API */
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extern int mmdvfs_set_step(enum MTK_SMI_BWC_SCEN scenario,
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enum mmdvfs_voltage_enum step);
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extern int mmdvfs_is_default_step_need_perf(void);
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extern void mmdvfs_mm_clock_switch_notify(int is_before, int is_to_high);
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#endif
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